{"title":"具有不同 JFET 宽度的六角形平面 SiC VDMOSFET 的特性和 UIS 研究","authors":"Hou-Cai Luo;Huan Wu;Jing-Ping Zhang;Bo-Feng Zheng;Lei Lang;Guo-Qi Zhang;Xian-Ping Chen","doi":"10.1109/TDMR.2024.3388482","DOIUrl":null,"url":null,"abstract":"The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L\n<inline-formula> <tex-math>${_{\\text {JFET}}} = 1.4\\mu $ </tex-math></inline-formula>\nm has the best HF-FOM (R\n<inline-formula> <tex-math>${_{\\text {on}}} \\times $ </tex-math></inline-formula>\nCgd) and HF-FOM (R\n<inline-formula> <tex-math>${_{\\text {on}}} \\times $ </tex-math></inline-formula>\nQgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"323-328"},"PeriodicalIF":2.5000,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width\",\"authors\":\"Hou-Cai Luo;Huan Wu;Jing-Ping Zhang;Bo-Feng Zheng;Lei Lang;Guo-Qi Zhang;Xian-Ping Chen\",\"doi\":\"10.1109/TDMR.2024.3388482\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L\\n<inline-formula> <tex-math>${_{\\\\text {JFET}}} = 1.4\\\\mu $ </tex-math></inline-formula>\\nm has the best HF-FOM (R\\n<inline-formula> <tex-math>${_{\\\\text {on}}} \\\\times $ </tex-math></inline-formula>\\nCgd) and HF-FOM (R\\n<inline-formula> <tex-math>${_{\\\\text {on}}} \\\\times $ </tex-math></inline-formula>\\nQgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"24 2\",\"pages\":\"323-328\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2024-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10499866/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10499866/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width
The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L
${_{\text {JFET}}} = 1.4\mu $
m has the best HF-FOM (R
${_{\text {on}}} \times $
Cgd) and HF-FOM (R
${_{\text {on}}} \times $
Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.
期刊介绍：
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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