{"title":"针对 130 纳米至 28 纳米节点及更高节点超大规模器件的离态 TDDB 下通用介质击穿建模","authors":"Tidjani Garba-Seybou;Alain Bravaix;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho","doi":"10.1109/TDMR.2024.3387271","DOIUrl":null,"url":null,"abstract":"This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor \n<inline-formula> <tex-math>$\\beta $ </tex-math></inline-formula>\n value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"174-183"},"PeriodicalIF":2.5000,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond\",\"authors\":\"Tidjani Garba-Seybou;Alain Bravaix;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho\",\"doi\":\"10.1109/TDMR.2024.3387271\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor \\n<inline-formula> <tex-math>$\\\\beta $ </tex-math></inline-formula>\\n value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"24 2\",\"pages\":\"174-183\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2024-04-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10506198/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10506198/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond
This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor
$\beta $
value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.
期刊介绍:
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.