{"title":"基于 6T XNOR 的新型低功耗全加法器和全减法器的设计以及各种加法器和减法器的比较","authors":"","doi":"10.30534/ijeter/2024/031242024","DOIUrl":null,"url":null,"abstract":"Portable high speed digital devices are an emerging area and the designing of such circuits in VLSI is the need of the hour. Arithmetic and logic functions are the main blocks of such designs. Adders and subtractors are used in complex data processing to perform arithmetic operations. Designing of adders and subtractor using 6T XNOR demonstrates Low power, high speed switching and also optimized Area by means of transistor count compared to conventional adders and subtractors. This paper presents novel approach for 6T XNOR based full adder and full subtractor circuits. The circuit realization has been performed using DSCH and waveforms are obtained by using Micro wind 3.1","PeriodicalId":13964,"journal":{"name":"International Journal of Emerging Trends in Engineering Research","volume":"2015 6","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Novel Low Power 6T XNOR based Full Adder and Full Subtractor and Comparison of Various Adders and Subtractors\",\"authors\":\"\",\"doi\":\"10.30534/ijeter/2024/031242024\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Portable high speed digital devices are an emerging area and the designing of such circuits in VLSI is the need of the hour. Arithmetic and logic functions are the main blocks of such designs. Adders and subtractors are used in complex data processing to perform arithmetic operations. Designing of adders and subtractor using 6T XNOR demonstrates Low power, high speed switching and also optimized Area by means of transistor count compared to conventional adders and subtractors. This paper presents novel approach for 6T XNOR based full adder and full subtractor circuits. The circuit realization has been performed using DSCH and waveforms are obtained by using Micro wind 3.1\",\"PeriodicalId\":13964,\"journal\":{\"name\":\"International Journal of Emerging Trends in Engineering Research\",\"volume\":\"2015 6\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Emerging Trends in Engineering Research\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.30534/ijeter/2024/031242024\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Emerging Trends in Engineering Research","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.30534/ijeter/2024/031242024","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"Engineering","Score":null,"Total":0}
Design of Novel Low Power 6T XNOR based Full Adder and Full Subtractor and Comparison of Various Adders and Subtractors
Portable high speed digital devices are an emerging area and the designing of such circuits in VLSI is the need of the hour. Arithmetic and logic functions are the main blocks of such designs. Adders and subtractors are used in complex data processing to perform arithmetic operations. Designing of adders and subtractor using 6T XNOR demonstrates Low power, high speed switching and also optimized Area by means of transistor count compared to conventional adders and subtractors. This paper presents novel approach for 6T XNOR based full adder and full subtractor circuits. The circuit realization has been performed using DSCH and waveforms are obtained by using Micro wind 3.1