{"title":"利用噪声分布测量电压的 ASIC 原型 SMAUG1 的设计与测量","authors":"Grzegorz Węgrzyn, Robert Szczygieł","doi":"10.1088/1748-0221/19/04/c04053","DOIUrl":null,"url":null,"abstract":"\n We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.","PeriodicalId":507814,"journal":{"name":"Journal of Instrumentation","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and measurements of SMAUG1, a prototype ASIC for voltage measurement using noise distribution\",\"authors\":\"Grzegorz Węgrzyn, Robert Szczygieł\",\"doi\":\"10.1088/1748-0221/19/04/c04053\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.\",\"PeriodicalId\":507814,\"journal\":{\"name\":\"Journal of Instrumentation\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Instrumentation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1088/1748-0221/19/04/c04053\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Instrumentation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1088/1748-0221/19/04/c04053","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and measurements of SMAUG1, a prototype ASIC for voltage measurement using noise distribution
We present the implementation of the indirect voltage measurement using a noise distribution algorithm [1] in the prototype application-specific integrated circuit (ASIC) SMAUG_ND_1 designed in CMOS 28 nm technology. The chip implements the matrix of 7×7 pixels with the size of 68×68 μm. Each pixel contains eight independent comparators implementing the described algorithm and optional correlated-double-sampling method. The paper describes the ASIC architecture and briefly presents preliminary test results and encountered problems.
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