TeleVM:适用于 RISC-V 架构的轻量级虚拟机

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-04-30 DOI:10.1109/LCA.2024.3394835
Tianzheng Li;Enfang Cui;Yuting Wu;Qian Wei;Yue Gao
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引用次数: 0

摘要

无服务器计算具有快速大规模部署和现收现付收费模式等优势,已成为云计算的重要范式。由于共享基础设施和多租户环境,无服务器应用程序对安全性有很高的要求。传统的虚拟机和容器无法完全满足无服务器应用程序的要求。因此,轻量级虚拟机技术应运而生,它既能减少开销和启动时间,又能确保安全。在这封信中,我们提出了针对 RISC-V 架构的轻量级虚拟机 TeleVM。TeleVM 可通过对 RISC-V 的管理程序扩展实现强隔离。与传统虚拟机相比,TeleVM 只实现了少量的 IO 设备和功能,可以有效减少内存开销和启动时间。我们通过实验比较了TeleVM和QEMU+KVM。与QEMU+KVM相比,TeleVM的启动时间和内存开销分别减少了74%和90%。这项工作进一步完善了 RISC-V 架构的云计算软件生态系统,促进了 RISC-V 架构在云计算场景中的应用。
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TeleVM: A Lightweight Virtual Machine for RISC-V Architecture
Serverless computing has become an important paradigm in cloud computing due to its advantages such as fast large-scale deployment and pay-as-you-go charging model. Due to shared infrastructure and multi-tenant environments, serverless applications have high security requirements. Traditional virtual machines and containers cannot fully meet the requirements of serverless applications. Therefore, lightweight virtual machine technology has emerged, which can reduce overhead and boot time while ensuring security. In this letter, we propose TeleVM, a lightweight virtual machine for RISC-V architecture. TeleVM can achieve strong isolation through the hypervisor extension of RISC-V. Compared with traditional virtual machines, TeleVM only implements a small number of IO devices and functions, which can effectively reduce memory overhead and boot time. We compared TeleVM and QEMU+KVM through experiments. Compared to QEMU+KVM, the boot time and memory overhead of TeleVM have decreased by 74% and 90% respectively. This work further improves the cloud computing software ecosystem of RISC-V architecture and promotes the use of RISC-V architecture in cloud computing scenarios.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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