VLSI architecture of stochastic genetic algorithm for real time training of deep neural network

In this letter, attempt has been made to successfully design a pipelined VLSI architecture for the computation of genetic algorithm (GA). The concept of stochastic computing is uniquely exploited in the proposed pipelined GA architecture to attain significant area and power efficiency with reasonably high speed of operation. The prototype 8-bit fixed point GA architecture is realised using VHDL on Xilinx Vivado 2020.3 and implemented on Zynq Ultrascale+ MPSoC (XCZU7EV-2FFVC1156) to train an arbitrary 4:3:2 fully connected neural network in real-time. The performance of the prototype GA architecture in case of real-time training of the neural network outshines the software and other existing GA architectures. The proposed GA-trained 4:3:2 network exhibits 6X reduction in training time and 720X increase in power efficiency, only at the cost of \(0.06\%\) reduction in accuracy with respect to other existing works and software in case of the image classification of MNIST data-set.