Omkar Phadke, Tae-Hyeon Kim, Yuan-Chun Luo, Shimeng Yu
{"title":"(铁电非挥发性电容式突触用于电荷域内存计算(特邀","authors":"Omkar Phadke, Tae-Hyeon Kim, Yuan-Chun Luo, Shimeng Yu","doi":"10.1149/11314.0003ecst","DOIUrl":null,"url":null,"abstract":"The ferroelectric field effect transistor (FeFET) can be configured in nvCAP mode to enable a small-signal capacitive readout. Operating the FeFET in nvCAP mode for Charge-domain Compute-in-Memory provides benefits such as reduced power consumption and suppressed read disturb. In this review article, working of FeFET in nvCAP mode is described. Further, the TCAD study results are summarized to optimize the FeFET structure for maximizing the device performance in nvCAP mode, where the gate area and the overlap region decides the ON and OFF state capacitance. Next, the reliability aspects of nvCAP are discussed. The FeFET in nvCAP demonstrates an initial endurance of 106 P/E cycles, which can be further extended by 100× by performing a recovery operation. The nvCAP device shows a retention of at least 1 day at 850C for the fresh, fatigued and recovered state of the device, making it a suitable candidate for Compute-in-Memory.","PeriodicalId":11473,"journal":{"name":"ECS Transactions","volume":"5 13","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"(Invited) Ferroelectric Nonvolatile Capacitive Synapse for Charge Domain Compute-in-Memory\",\"authors\":\"Omkar Phadke, Tae-Hyeon Kim, Yuan-Chun Luo, Shimeng Yu\",\"doi\":\"10.1149/11314.0003ecst\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ferroelectric field effect transistor (FeFET) can be configured in nvCAP mode to enable a small-signal capacitive readout. Operating the FeFET in nvCAP mode for Charge-domain Compute-in-Memory provides benefits such as reduced power consumption and suppressed read disturb. In this review article, working of FeFET in nvCAP mode is described. Further, the TCAD study results are summarized to optimize the FeFET structure for maximizing the device performance in nvCAP mode, where the gate area and the overlap region decides the ON and OFF state capacitance. Next, the reliability aspects of nvCAP are discussed. The FeFET in nvCAP demonstrates an initial endurance of 106 P/E cycles, which can be further extended by 100× by performing a recovery operation. The nvCAP device shows a retention of at least 1 day at 850C for the fresh, fatigued and recovered state of the device, making it a suitable candidate for Compute-in-Memory.\",\"PeriodicalId\":11473,\"journal\":{\"name\":\"ECS Transactions\",\"volume\":\"5 13\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-05-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ECS Transactions\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1149/11314.0003ecst\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ECS Transactions","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1149/11314.0003ecst","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
(Invited) Ferroelectric Nonvolatile Capacitive Synapse for Charge Domain Compute-in-Memory
The ferroelectric field effect transistor (FeFET) can be configured in nvCAP mode to enable a small-signal capacitive readout. Operating the FeFET in nvCAP mode for Charge-domain Compute-in-Memory provides benefits such as reduced power consumption and suppressed read disturb. In this review article, working of FeFET in nvCAP mode is described. Further, the TCAD study results are summarized to optimize the FeFET structure for maximizing the device performance in nvCAP mode, where the gate area and the overlap region decides the ON and OFF state capacitance. Next, the reliability aspects of nvCAP are discussed. The FeFET in nvCAP demonstrates an initial endurance of 106 P/E cycles, which can be further extended by 100× by performing a recovery operation. The nvCAP device shows a retention of at least 1 day at 850C for the fresh, fatigued and recovered state of the device, making it a suitable candidate for Compute-in-Memory.