Design of a Ternary Logic Processor Using CNTFET Technology

The design of a Ternary Logic Processor using CNTFETs (Carbon-Nanotube-Field-Effect-Transistor) is a challenging task, but it also has the potential to offer significant advantages over the traditional binary logic processors based on CMOS (Complementary-Metal-Oxide-Semiconductor) technology. This paper presents the design and implementation of a Ternary Logic Processor (TLP) using CNTFETs. The TLP is a single-cycle processor that operates on three-trit data. An Instruction Set Architecture (ISA) is defined, at first, for this TLP that consists of instructions of the Register type, Load-store type, Immediate type, and branch type. Based on the ISA, the architecture of the CNTFET-based TLP is proposed and the transistor level designs of the TLPs’ fundamental blocks like the Ternary Instruction Fetch (TIF), Ternary Register File (TRF), Ternary Arithmetic and Logic Unit (TALU) and Ternary Data Memory (TDM) are presented. HSPICE simulations using a standard CNTFET model, are performed for the TLP and the TLPs’ individual blocks and the performance parameters like the power consumption, propagation delay, and the number of CNTFETs required are calculated. In addition to this, the functionality of the processor is verified using a few of the standard programs.