先进 CMOS 设备应用中硅和硅介电薄膜的干法蚀刻和沉积工艺建模回顾与展望

Nobuyuki Kuboi
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引用次数: 0

摘要

硅和硅介电薄膜的干法蚀刻和沉积是实现先进互补金属氧化物半导体(CMOS)器件高性能的关键工艺。为了准确预测和控制这些工艺特性在量产过程中的波动,干法工艺模拟技术必须考虑各种因素。这些因素包括等离子体腔壁相互作用的波动、副产品对临界尺寸的影响、硅凹槽对晶圆开孔面积比和局部图案结构的依赖性、与特征尺度剖面相关的等离子体诱发损伤的随时间变化的分布,以及密度、渗透性和粘附性等薄膜特性。解决这些问题可以克服传统模拟所存在的问题,因为传统模拟缺乏大规模生产所需的精度。本文回顾了这些先进的模拟技术,并从融合物理模型与机器学习的角度进行了讨论,同时结合了制造设备的实时监控,即所谓的过程信息学。预计这种方法将开创全数字双胞胎时代。
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Review and perspective of dry etching and deposition process modeling of Si and Si dielectric films for advanced CMOS device applications
Dry etching and deposition of Si and Si dielectric films are critical processes for achieving of high performance in advanced complementary metal-oxide-semiconductor (CMOS) devices. To accurately predict and control fluctuations in these process properties during mass production, it is essential that dry process simulation technology considers various factors. These include fluctuations in plasma-chamber wall interaction, effects of by-products on critical dimensions, Si recess dependence on wafer open area ratios and local pattern structures, the time-dependent distribution of plasma-induced damage associated with feature-scale profiles, and film properties such as density, permeability, and adhesion. Addressing these considerations can overcome issues with conventional simulations that lack the accuracy required for mass production. This paper reviews these advanced simulation technologies and discusses the perspective of fusion physical models with machine learning, incorporating real-time monitoring in manufacturing equipment, known as process informatics. This approach is anticipated to usher in the era of full digital twins.
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