Yaw A. Mensah;Sunil G. Rao;Jeffrey W. Teng;John D. Cressler
{"title":"具有双驱动内核的 W 波段叠频四倍频器,排水效率达到 10.3","authors":"Yaw A. Mensah;Sunil G. Rao;Jeffrey W. Teng;John D. Cressler","doi":"10.1109/LMWT.2024.3392576","DOIUrl":null,"url":null,"abstract":"A \n<inline-formula> <tex-math>$W$ </tex-math></inline-formula>\n-band stacked quadrupler with a dual-driven second-stage doubler is presented that, to the best of the authors’ knowledge, demonstrates the highest \n<inline-formula> <tex-math>$W$ </tex-math></inline-formula>\n-band drain efficiency in silicon while maintaining a competitive output power and harmonic rejection. Implemented in a 90-nm SiGe BiCMOS process, the proposed topology circumvents the need for an interstage balun by using a pair of push–push doublers (PPDs), whose input signals are 90° out-of-phase, as an input stage to drive a third, dual-driven push–push doubler. The stacked dual-driven second stage allows for current reuse between the two stages while maintaining a large input swing on the output stage, promoting a highly efficient design. As a result, the quadrupler achieves a peak conversion gain of 2.2 dB, a peak output power of 6.8 dBm, a harmonic rejection of greater than 31 dBc, and a peak drain efficiency of 10.3%.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A W-Band Stacked Frequency Quadrupler With a Dual-Driven Core Achieving 10.3% Drain Efficiency\",\"authors\":\"Yaw A. Mensah;Sunil G. Rao;Jeffrey W. Teng;John D. Cressler\",\"doi\":\"10.1109/LMWT.2024.3392576\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A \\n<inline-formula> <tex-math>$W$ </tex-math></inline-formula>\\n-band stacked quadrupler with a dual-driven second-stage doubler is presented that, to the best of the authors’ knowledge, demonstrates the highest \\n<inline-formula> <tex-math>$W$ </tex-math></inline-formula>\\n-band drain efficiency in silicon while maintaining a competitive output power and harmonic rejection. Implemented in a 90-nm SiGe BiCMOS process, the proposed topology circumvents the need for an interstage balun by using a pair of push–push doublers (PPDs), whose input signals are 90° out-of-phase, as an input stage to drive a third, dual-driven push–push doubler. The stacked dual-driven second stage allows for current reuse between the two stages while maintaining a large input swing on the output stage, promoting a highly efficient design. As a result, the quadrupler achieves a peak conversion gain of 2.2 dB, a peak output power of 6.8 dBm, a harmonic rejection of greater than 31 dBc, and a peak drain efficiency of 10.3%.\",\"PeriodicalId\":73297,\"journal\":{\"name\":\"IEEE microwave and wireless technology letters\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-04-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE microwave and wireless technology letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10510459/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"0\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10510459/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A W-Band Stacked Frequency Quadrupler With a Dual-Driven Core Achieving 10.3% Drain Efficiency
A
$W$
-band stacked quadrupler with a dual-driven second-stage doubler is presented that, to the best of the authors’ knowledge, demonstrates the highest
$W$
-band drain efficiency in silicon while maintaining a competitive output power and harmonic rejection. Implemented in a 90-nm SiGe BiCMOS process, the proposed topology circumvents the need for an interstage balun by using a pair of push–push doublers (PPDs), whose input signals are 90° out-of-phase, as an input stage to drive a third, dual-driven push–push doubler. The stacked dual-driven second stage allows for current reuse between the two stages while maintaining a large input swing on the output stage, promoting a highly efficient design. As a result, the quadrupler achieves a peak conversion gain of 2.2 dB, a peak output power of 6.8 dBm, a harmonic rejection of greater than 31 dBc, and a peak drain efficiency of 10.3%.