2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues

This paper presents circuit for $2\times \text{VDD}$ signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for $2\times \text{VDD}$ signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.