用于 FPGA 实现的基于 DSP 的高速低功耗 TRNG

IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-07-01 DOI:10.1109/TCSII.2024.3421323
Fabio Frustaci;Fanny Spagnolo;Pasquale Corsonello;Stefania Perri
{"title":"用于 FPGA 实现的基于 DSP 的高速低功耗 TRNG","authors":"Fabio Frustaci;Fanny Spagnolo;Pasquale Corsonello;Stefania Perri","doi":"10.1109/TCSII.2024.3421323","DOIUrl":null,"url":null,"abstract":"This brief presents an effective way to design high-throughput and low-power True Random Number Generators (TRNGs) for Field Programmable Gate Array (FPGA)-based digital systems. The proposed design makes an unconventional usage of the Digital Signal Processing (DSP) slice embedded within the AMD-Xilinx FPGA devices to implement high jitter ring oscillators as entropy sources for efficient TRNG designs. Thanks to its wide bit-width output, several configurations can be enabled to group multiple oscillators within a single DSP slice. As a result, a TRNG designed through the proposed scheme outputs up to 4 random bits per clock cycle, thus leading to a considerably high-throughput, while exploiting an ultra-compact architecture. When implemented on the AMD-Xilinx Zynq XC7Z020 System on Chip (SoC), the new architecture achieves a throughput of \n<inline-formula> <tex-math>$800\\times 10{^{{6}}}$ </tex-math></inline-formula>\n bit/sec and an energy consumption of only 22 pJ/bit. When compared to state-of-the-art competitors it achieves a throughput rate up to \n<inline-formula> <tex-math>$2.6\\times $ </tex-math></inline-formula>\n higher and an energy consumption up to \n<inline-formula> <tex-math>$8\\times $ </tex-math></inline-formula>\n lower. The new TRNG has been validated by means of the NIST SP 800-22, the NIST 800 90B and the AIS statistical tests.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4964-4968"},"PeriodicalIF":4.0000,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10578016","citationCount":"0","resultStr":"{\"title\":\"A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations\",\"authors\":\"Fabio Frustaci;Fanny Spagnolo;Pasquale Corsonello;Stefania Perri\",\"doi\":\"10.1109/TCSII.2024.3421323\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents an effective way to design high-throughput and low-power True Random Number Generators (TRNGs) for Field Programmable Gate Array (FPGA)-based digital systems. The proposed design makes an unconventional usage of the Digital Signal Processing (DSP) slice embedded within the AMD-Xilinx FPGA devices to implement high jitter ring oscillators as entropy sources for efficient TRNG designs. Thanks to its wide bit-width output, several configurations can be enabled to group multiple oscillators within a single DSP slice. As a result, a TRNG designed through the proposed scheme outputs up to 4 random bits per clock cycle, thus leading to a considerably high-throughput, while exploiting an ultra-compact architecture. When implemented on the AMD-Xilinx Zynq XC7Z020 System on Chip (SoC), the new architecture achieves a throughput of \\n<inline-formula> <tex-math>$800\\\\times 10{^{{6}}}$ </tex-math></inline-formula>\\n bit/sec and an energy consumption of only 22 pJ/bit. When compared to state-of-the-art competitors it achieves a throughput rate up to \\n<inline-formula> <tex-math>$2.6\\\\times $ </tex-math></inline-formula>\\n higher and an energy consumption up to \\n<inline-formula> <tex-math>$8\\\\times $ </tex-math></inline-formula>\\n lower. The new TRNG has been validated by means of the NIST SP 800-22, the NIST 800 90B and the AIS statistical tests.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"71 12\",\"pages\":\"4964-4968\"},\"PeriodicalIF\":4.0000,\"publicationDate\":\"2024-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10578016\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10578016/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10578016/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本简介介绍了一种为基于现场可编程门阵列(FPGA)的数字系统设计高吞吐量、低功耗真正随机数发生器(TRNG)的有效方法。所提出的设计非常规地利用了 AMD-Xilinx FPGA 器件中嵌入的数字信号处理 (DSP) 片,将高抖动环形振荡器作为高效 TRNG 设计的熵源。得益于其宽位宽输出,可在单个 DSP 片内启用多种配置来组合多个振荡器。因此,通过所提方案设计的 TRNG 每个时钟周期最多可输出 4 个随机比特,从而在利用超紧凑架构的同时实现了相当高的吞吐量。在 AMD-Xilinx Zynq XC7Z020 片上系统(SoC)上实现时,新架构的吞吐量达到了 $800/times 10{^{{6}}$ 比特/秒,能耗仅为 22 pJ/比特。与最先进的竞争对手相比,它的吞吐率最高可提高 2.6 times $,能耗最高可降低 8 times $。新型 TRNG 已通过 NIST SP 800-22、NIST 800 90B 和 AIS 统计测试验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations
This brief presents an effective way to design high-throughput and low-power True Random Number Generators (TRNGs) for Field Programmable Gate Array (FPGA)-based digital systems. The proposed design makes an unconventional usage of the Digital Signal Processing (DSP) slice embedded within the AMD-Xilinx FPGA devices to implement high jitter ring oscillators as entropy sources for efficient TRNG designs. Thanks to its wide bit-width output, several configurations can be enabled to group multiple oscillators within a single DSP slice. As a result, a TRNG designed through the proposed scheme outputs up to 4 random bits per clock cycle, thus leading to a considerably high-throughput, while exploiting an ultra-compact architecture. When implemented on the AMD-Xilinx Zynq XC7Z020 System on Chip (SoC), the new architecture achieves a throughput of $800\times 10{^{{6}}}$ bit/sec and an energy consumption of only 22 pJ/bit. When compared to state-of-the-art competitors it achieves a throughput rate up to $2.6\times $ higher and an energy consumption up to $8\times $ lower. The new TRNG has been validated by means of the NIST SP 800-22, the NIST 800 90B and the AIS statistical tests.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程:电子与电气
CiteScore
7.90
自引率
20.50%
发文量
883
审稿时长
3.0 months
期刊介绍: TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.
期刊最新文献
Table of Contents IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information Table of Contents Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium IEEE Circuits and Systems Society Information
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1