Approximate Floating Point Precise Carry Prediction Adder for FIR Filter Applications

Approximate computing plays a crucial role in faster operation for large-scale data computation in error-resilient applications. An approximate adder is a digital circuit that performs addition with less accuracy to achieve faster processing time and lower hardware overhead. This approach is well suited for error-tolerant applications where minor errors in the output are acceptable. In this paper, an approximate carry prediction adder (ACPA) is proposed to add the mantissa in a 32-bit single precision floating point adder, termed as approximate floating point precise carry prediction adder (AFPCPA). The proposed ACPA utilizes a carry prediction circuit to generate a precise carry for the precise part leading to an increase in accuracy. The error characteristics and hardware utilization of AFPCPA and other existing approximate adder architectures are compared. The results show that the proposed AFPCPA vide, on average, 50.56%, 59.66%, 56.13%, and 81.40% reduction in standard deviation, mean absolute error, normalized mean error distance, and mean square error, respectively. In addition, the proposed AFPCPA shows on average, 18.97% and 6.68% lesser hardware utilization and delay, respectively compared to existing approximate adder architectures and accurate adder. Finally, a 3-tap FIR Filter is designed using the proposed AFPCPA and compared with existing architectures.