无乘法器忆阻器仿真器及其实验结果和神经形态应用

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Analog Integrated Circuits and Signal Processing Pub Date : 2024-07-04 DOI:10.1007/s10470-024-02286-9
B. Suresha, Chandra Shankar, S. B. Rudraswamy
{"title":"无乘法器忆阻器仿真器及其实验结果和神经形态应用","authors":"B. Suresha,&nbsp;Chandra Shankar,&nbsp;S. B. Rudraswamy","doi":"10.1007/s10470-024-02286-9","DOIUrl":null,"url":null,"abstract":"<div><p>This research article presents a meminductor emulator without multiplier using double output second generation current conveyor (DO-CCII) and operational trans-conductance amplifiers (OTA) and minimum numbers of passive elements. The mathematical expression of meminductor is obtained and verified through various simulation i.e., hysteresis analysis, non-volatile analysis and process corner analysis. Also, presented post-layout simulation of silicon components (DO-CCII and OTA). Application of meminductor emulator as Amoeba behaviour is also incorporated in the Neuromorphic circuit. Furthermore, an experimental setup was also build using the off the shelf ICs AD844AN (for DO-CCII) and CA3080EZ (for OTA) to examine the experimental results. The proposed meminductor emulator is simulated in Cadence Virtuoso tool using standard CMOS 90 nm technology.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A multiplier-less meminductor emulator with experimental results and neuromorphic application\",\"authors\":\"B. Suresha,&nbsp;Chandra Shankar,&nbsp;S. B. Rudraswamy\",\"doi\":\"10.1007/s10470-024-02286-9\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This research article presents a meminductor emulator without multiplier using double output second generation current conveyor (DO-CCII) and operational trans-conductance amplifiers (OTA) and minimum numbers of passive elements. The mathematical expression of meminductor is obtained and verified through various simulation i.e., hysteresis analysis, non-volatile analysis and process corner analysis. Also, presented post-layout simulation of silicon components (DO-CCII and OTA). Application of meminductor emulator as Amoeba behaviour is also incorporated in the Neuromorphic circuit. Furthermore, an experimental setup was also build using the off the shelf ICs AD844AN (for DO-CCII) and CA3080EZ (for OTA) to examine the experimental results. The proposed meminductor emulator is simulated in Cadence Virtuoso tool using standard CMOS 90 nm technology.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.2000,\"publicationDate\":\"2024-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-024-02286-9\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-024-02286-9","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

本文介绍了一种无乘法器的忆阻器仿真器,它使用了双输出第二代电流传送器(DO-CCII)和运算跨导放大器(OTA),并使用了最少的无源元件。通过各种仿真,即磁滞分析、非易失分析和工艺转角分析,获得并验证了忆阻器的数学表达式。此外,还介绍了硅元件的布局后仿真(DO-CCII 和 OTA)。在神经形态电路中还应用了作为阿米巴行为的忆阻器仿真器。此外,还利用现成的集成电路 AD844AN(用于 DO-CCII)和 CA3080EZ(用于 OTA)建立了一个实验装置,以检验实验结果。利用标准 CMOS 90 纳米技术,在 Cadence Virtuoso 工具中对所提出的忆阻器仿真器进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

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A multiplier-less meminductor emulator with experimental results and neuromorphic application

This research article presents a meminductor emulator without multiplier using double output second generation current conveyor (DO-CCII) and operational trans-conductance amplifiers (OTA) and minimum numbers of passive elements. The mathematical expression of meminductor is obtained and verified through various simulation i.e., hysteresis analysis, non-volatile analysis and process corner analysis. Also, presented post-layout simulation of silicon components (DO-CCII and OTA). Application of meminductor emulator as Amoeba behaviour is also incorporated in the Neuromorphic circuit. Furthermore, an experimental setup was also build using the off the shelf ICs AD844AN (for DO-CCII) and CA3080EZ (for OTA) to examine the experimental results. The proposed meminductor emulator is simulated in Cadence Virtuoso tool using standard CMOS 90 nm technology.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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