用于安全关键型网络物理系统的基于可靠状态机的硬件架构的形式化验证:分析、设计与实现

Shawkat Sabah Khairullah
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引用次数: 0

摘要

随着人们对在工业自动化、航空航天和汽车行业等安全关键网络物理系统(CPS)中嵌入数字设备的兴趣与日俱增,人们开始关注提出可验证的可靠架构。高水平的形式化验证和容错是可靠的 CPS 系统的要求,以确保系统设计符合规范并验证安全属性。本文以状态机、验证和容错概念为基础,开发了一种新型的形式化可验证和容错硬件架构。它分为四个模型:分析模型包括用户定义的功能要求;设计模型,利用有限状态机对系统行为进行建模,并通过 NuSMV 校验工具进行测试;实现模型,在波形上模拟测试用例,根据要求验证设计;验证模型,利用数学形式线性时间和计算树逻辑验证功能和关键属性,以证明符合要求并检测错误。该系统以铁路联锁系统(RIS)为案例,使用时序逻辑来制定所需的属性,并使用符号模型验证器(SMV)来证明执行的正确性。仿真结果证明了该架构在验证关键属性和通过多数表决电路检测设计故障方面的有效性。提出的架构已在 Altera FPGA 可编程芯片中合成,逻辑元素占 33%,面积开销占 52%,频率为 100 MHz。该系统确实满足了其可靠性要求,最低可靠性为 91.333687 x \({10}^{-2}\),故障率为每小时 0.2 次,故障时间为 60 分钟。最后,我们认为采用这种架构将增强 CPS 系统的可信度和认证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

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Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation

With the increasing interest in embedding digital devices in safety-critical cyber-physical systems (CPSs), such as industrial automation, aerospace, and automotive industries, attention has been directed toward proposing verifiable and reliable architectures. Prominent levels of formal verification and fault-tolerance are a requirement in dependable CPS systems to ensure system design meet the specifications and verify safety properties. In this paper, a novel formal verifiable and fault-tolerant hardware architecture uses the concepts of state machine, verification, and fault-tolerance as a foundation is developed. It is divided into four models: analysis model includes the functional requirements defined by the user, design model, the finite state machine is utilized to model the systems behavior which is tested by the NuSMV checker tool, implementation model simulates test cases on waveforms to validate the design against the requirements and verification model verifies functional and critical properties using mathematical formal linear time and computation tree logic to prove compliance with requirements and detect errors. The system uses temporal logic to formulate the required properties for a railway interlocking system (RIS) as a case study and symbolic model verifier (SMV) to demonstrate the correct execution. From the simulation results, the effectiveness of the architecture is proved for verifying critical properties and detecting design faults through majority voting circuits. The proposed architecture has been synthesized in the Altera FPGA programmable chip with logic elements 33%, 52% area overhead, and frequency as 100 MHz. The system does meet its reliability requirements with the lowest reliability 91.333687 x \({10}^{-2}\) and failure rate 0.2 failure per hour at time 60 min. Finally, we think that adopting this architecture will enhance the trustworthiness and certification of CPS systems.

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