A 20-Gb/s 4-tap time-domain DFE with pulse width modulation for a DQ-DQS matched parallel receiver

A 4-tap time-domain decision feedback equalizer (TD-DFE) is presented to implement a multi-tap DFE in a matched DQ (data)-DQS (strobe) tree architecture. Traditionally, matched architecture holds an advantage in terms of power noise immunity, but it suffers from low-speed performance due to the unavailability of decision feedback equalizer (DFE) applications. By adopting the proposed TD-DFE, both high-speed operation and power noise immunity can be achieved within the matched architecture. An 8-DQ parallel receiver with the proposed 4-tap TD-DFE, designed in 28 nm CMOS, achieves a data rate of 20 Gb/s with 0.6 UI eye-opening even with 215 mV power fluctuations.