适用于 16 美元多 MU-MIMO 系统的高吞吐量建设性干扰前置编码器

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-12 DOI:10.1109/TVLSI.2024.3423341
Yu-Cheng Lin;Ren-Hao Chiou;Chia-Hsiang Yang
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引用次数: 0

摘要

在多用户多输入多输出(MU-MIMO)下行链路系统中,由于数据在相同的时频资源上同时传输,用户很容易受到用户间干扰(IUI)的影响。传统的预编码算法旨在消除 IUI。然而,建设性干扰(CI)预编码可以利用 IUI 实现更好的误差性能。本文介绍了一种高吞吐量的 CI 预编码器。通过对算法和架构层进行设计优化,乘法的复杂度降低了 81.6%。由于收敛的迭代次数不同,因此采用了动态资源分配,以最大限度地利用资源来支持每种调制模式:4-QAM 模式采用时间多路复用,16-QAM 模式采用并行处理。拟议的符号更新器还能提高调度效率。作为概念验证,基于40纳米CMOS技术设计了一款CI前置编码器芯片,可支持高达16美元的MU-MIMO系统。与传统的正则化零强迫(RZF)方案相比,4-QAM 和 16-QAM 在误码率(BER)$= 10^{-4}$ 时的性能分别提高了 10.7 和 12.5 dB。在时钟频率为 200 MHz 的 $16 \times $ MU-MIMO 配置下,前置编码器的最大吞吐量为 3.2 Gb/s。
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A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems
In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to $16 \times $ MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) $= 10^{-4}$ are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the $16 \times $ MU-MIMO configuration.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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