采用 180 纳米 CMOS 的 81.5dB SNDR、2.5 MHz 带宽增量式连续时间三角积分 ADC

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2024-06-11 DOI:10.1109/LSSC.2024.3412634
Aswani Kumar Unnam;Paramita Banerjee;Nagendra Krishnapura
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引用次数: 0

摘要

将连续时间三角积分模数转换器 (ADC) 改用于高采样率下的增量操作会降低噪声和失真,这是由于调制器在复位时可能过载,以及在复位阶段输入电流流过复位开关造成非线性残留。这表明,输入电流和 DAC 电流必须同时开始流过第一个积分电容器,以尽量减少过载的可能性。第一个积分器复位必须在 DAC 脉冲开始之前释放。必须使用前馈路径,以确保 DAC 输出从一开始就接近输入信号。在复位阶段阻止输入电流流经复位开关,可消除非线性残差的影响。采用上述技术的 320 MS/s 四阶增量三角积分 ADC 原型采用 180 纳米工艺制造,在 2.5 MHz 带宽内具有 90 dB 动态范围、82 dB SNDR 和 84.5 dB SNR。其 1.8V 电源功耗为 46.3 mW,占地面积为 0.7 mm2。
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An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS
Adapting a continuous time delta-sigma analog-to-digital converter (ADC) for incremental operation at high sampling rates degrades the noise and distortion due to potential overload of the modulator as it comes out of reset and nonlinear residue on the reset switch due to input current flowing through it in the reset phase. It is shown that the input and DAC currents must simultaneously begin to flow through the first integrating capacitor to minimize the possibility of overload. The first integrator reset has to be released just before the start of the DAC pulse. A feedforward path must be used to ensure that the DAC output is close to the input signal from the beginning. Blocking the input current from flowing through the reset switch in the reset phase eliminates the effect of the nonlinear residue. A 320 MS/s fourth-order incremental delta-sigma ADC prototype in an 180nm process using the above techniques has 90 dB dynamic range, 82 dB SNDR, and 84.5 dB SNR in a 2.5 MHz bandwidth. It consumes 46.3 mW from a 1.8V supply and occupies 0.7 mm2.
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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