Model-Based Study on the Limit of the Dynamic Load Regulation Performance of a Digital Low Dropout Regulator

A digital low dropout (DLDO) regulator is one of the most critical building blocks in on-chip power management for its technology portability, voltage scalability, and other benefits associated with digital-oriented design. A key metric of DLDOs is the dynamic load regulation performance, often measured as the maximum current that a DLDO can quickly supply upon a significant load step under a voltage droop constraint (usually 10% of the output voltage). Previous works focused on architecture and circuit techniques to improve this metric. However, limited research focuses on the model development for the dynamic load regulation performance. To fill this gap, in this article, we propose the analytical models of the maximum load current of the standard DLDOs employing feedback and feedforward control laws. The developed models shed light on the impact of various design parameters on the total load current of a DLDO, with which both circuit and system designers can navigate the design space quickly and effectively.