IRIS:跨平台异构计算的性能便携框架

IF 5.6 2区 计算机科学 Q1 COMPUTER SCIENCE, THEORY & METHODS IEEE Transactions on Parallel and Distributed Systems Pub Date : 2024-07-19 DOI:10.1109/TPDS.2024.3429010
Jungwon Kim;Seyong Lee;Beau Johnston;Jeffrey S. Vetter
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引用次数: 0

摘要

从边缘到超大规模,计算机架构正变得越来越异构和复杂。这些系统通常具有胖节点、多核 CPU 和多个硬件加速器(如 GPU、FPGA 和 DSP)。这种复杂性给编程系统和性能可移植性带来了危机。一些编程系统正在努力应对这些挑战,但日益增长的架构多样性正迫使软件栈和应用程序针对每种架构进行专门化。正如我们所展示的,所有这些方法在发现、执行、调度和数据协调方面都严重依赖于其软件框架。为了应对这一挑战,我们认为一个更加敏捷和主动的软件框架对于提高性能可移植性和用户生产率至关重要。为此,我们设计并实施了 IRIS:一个性能可移植的跨平台异构计算框架。IRIS 可以发现可用资源,在同一执行过程中同时管理多个不同的编程平台(如 CUDA、Hexagon、HIP、Level Zero、OpenCL、OpenMP),尊重数据依赖关系,主动协调数据移动,并提供用户可配置的调度。为了简化数据移动,IRIS 在不同异构设备之间引入了具有宽松一致性的共享虚拟设备内存。IRIS 还使用多面体模型添加了内核工作负载自动分区技术,从而可以为各种设备调整内核大小。我们在三种架构(从高通 Snapdragon 到 Summit 超级计算机节点)上进行的评估表明,IRIS 在各种不同的异构架构中提高了可移植性,其开销可忽略不计。
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IRIS: A Performance-Portable Framework for Cross-Platform Heterogeneous Computing
From edge to exascale, computer architectures are becoming more heterogeneous and complex. The systems typically have fat nodes, with multicore CPUs and multiple hardware accelerators such as GPUs, FPGAs, and DSPs. This complexity is causing a crisis in programming systems and performance portability. Several programming systems are working to address these challenges, but the increasing architectural diversity is forcing software stacks and applications to be specialized for each architecture. As we show, all of these approaches critically depend on their software framework for discovery, execution, scheduling, and data orchestration. To address this challenge, we believe that a more agile and proactive software framework is essential to increase performance portability and improve user productivity. To this end, we have designed and implemented IRIS: a performance-portable framework for cross-platform heterogeneous computing. IRIS can discover available resources, manage multiple diverse programming platforms (e.g., CUDA, Hexagon, HIP, Level Zero, OpenCL, OpenMP) simultaneously in the same execution, respect data dependencies, orchestrate data movement proactively, and provide for user-configurable scheduling. To simplify data movement, IRIS introduces a shared virtual device memory with relaxed consistency among different heterogeneous devices. IRIS also adds an automatic kernel workload partitioning technique using the polyhedral model so that it can resize kernels for a wide range of devices. Our evaluation on three architectures, ranging from Qualcomm Snapdragon to a Summit supercomputer node, shows that IRIS improves portability across a wide range of diverse heterogeneous architectures with negligible overhead.
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来源期刊
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems 工程技术-工程:电子与电气
CiteScore
11.00
自引率
9.40%
发文量
281
审稿时长
5.6 months
期刊介绍: IEEE Transactions on Parallel and Distributed Systems (TPDS) is published monthly. It publishes a range of papers, comments on previously published papers, and survey articles that deal with the parallel and distributed systems research areas of current importance to our readers. Particular areas of interest include, but are not limited to: a) Parallel and distributed algorithms, focusing on topics such as: models of computation; numerical, combinatorial, and data-intensive parallel algorithms, scalability of algorithms and data structures for parallel and distributed systems, communication and synchronization protocols, network algorithms, scheduling, and load balancing. b) Applications of parallel and distributed computing, including computational and data-enabled science and engineering, big data applications, parallel crowd sourcing, large-scale social network analysis, management of big data, cloud and grid computing, scientific and biomedical applications, mobile computing, and cyber-physical systems. c) Parallel and distributed architectures, including architectures for instruction-level and thread-level parallelism; design, analysis, implementation, fault resilience and performance measurements of multiple-processor systems; multicore processors, heterogeneous many-core systems; petascale and exascale systems designs; novel big data architectures; special purpose architectures, including graphics processors, signal processors, network processors, media accelerators, and other special purpose processors and accelerators; impact of technology on architecture; network and interconnect architectures; parallel I/O and storage systems; architecture of the memory hierarchy; power-efficient and green computing architectures; dependable architectures; and performance modeling and evaluation. d) Parallel and distributed software, including parallel and multicore programming languages and compilers, runtime systems, operating systems, Internet computing and web services, resource management including green computing, middleware for grids, clouds, and data centers, libraries, performance modeling and evaluation, parallel programming paradigms, and programming environments and tools.
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