Pub Date : 2026-02-27DOI: 10.1109/TPDS.2026.3668417
Huihuang Qin;Shuangwu Chen;Zian Wang;Tao Zhang;Ziyang Zou;Xiaobin Tan;Shiyin Zhu;Jian Yang
The massive parameter scale of sparsely-activated Mixture-of-Experts (MoE) models necessitates distributed training with hybrid parallelism. Placing such training tasks, i.e. mapping the logical partitions of an MoE model to available physical NPUs, is challenging. Due to the bandwidth and latency discrepancies between intra- and inter- Pods, the cross-Pod communication usually becomes a bottleneck. The high dispersion of NPUs in multi-tenant clusters exacerbates this issue further. However, a paucity of studies has considered the cross-Pod model placement problem. To address this challenge, we propose a novel model placement scheme tailored for MoE model training with hybrid parallelism in multi-tenant clusters. By quantifying the cross-Pod communication overhead incurred during MoE model training, the model placement is formulated as a 0-1 integer quadratic problem, which is NP hard. Motivated by the traffic difference between different parallelism, we decompose this problem into two subproblems. To solve the subproblems, we propose a lightweight two-stage algorithm based on Best-Fit strategy and neighborhood search. Experiments under different models and network topologies show that our model placement scheme can reduce cross-Pod traffic by 35.9% and cut communication time by 18.7% compared to state-of-the-art methods.
{"title":"Reducing Cross-Pod Communication Overhead for MoE Model Training With Hybrid Parallelism in Multi-Tenant Clusters","authors":"Huihuang Qin;Shuangwu Chen;Zian Wang;Tao Zhang;Ziyang Zou;Xiaobin Tan;Shiyin Zhu;Jian Yang","doi":"10.1109/TPDS.2026.3668417","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3668417","url":null,"abstract":"The massive parameter scale of sparsely-activated Mixture-of-Experts (MoE) models necessitates distributed training with hybrid parallelism. Placing such training tasks, i.e. mapping the logical partitions of an MoE model to available physical NPUs, is challenging. Due to the bandwidth and latency discrepancies between intra- and inter- Pods, the cross-Pod communication usually becomes a bottleneck. The high dispersion of NPUs in multi-tenant clusters exacerbates this issue further. However, a paucity of studies has considered the cross-Pod model placement problem. To address this challenge, we propose a novel model placement scheme tailored for MoE model training with hybrid parallelism in multi-tenant clusters. By quantifying the cross-Pod communication overhead incurred during MoE model training, the model placement is formulated as a 0-1 integer quadratic problem, which is NP hard. Motivated by the traffic difference between different parallelism, we decompose this problem into two subproblems. To solve the subproblems, we propose a lightweight two-stage algorithm based on Best-Fit strategy and neighborhood search. Experiments under different models and network topologies show that our model placement scheme can reduce cross-Pod traffic by 35.9% and cut communication time by 18.7% compared to state-of-the-art methods.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 5","pages":"1062-1078"},"PeriodicalIF":6.0,"publicationDate":"2026-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147440670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deep neural networks (DNNs) dominate workloads on cloud and edge platforms. Meanwhile, the hardware platform towards the heterogeneous system with various accelerators. By mapping layers to their differentpreferred accelerators, the computation cost of each layer can be reduced. While mapping these layers on the same accelerator can reduce the inter-accelerator communication cost. These two costs are often competing and difficult to optimize simultaneously. Therefore, the core challenge in achieving efficient execution of DNN workloads on heterogeneous systems is: how to map layers to achieve the best trade-off between computation and communication costs. Existing works group layers into blocks and perform block-wise mapping to reduce inter-layer communication within blocks. However, when grouping layers, they typically rely on model-agnostic rules, which fail to hide critical inter-layer communication within blocks for diverse DNNs. Moreover, after block mapping, the lack of intra-block resource allocation further increases computation cost of block. In this paper, we propose GHCoM, a novel block-wise mapping framework for exploring the effective cost trade-offs. GHCoM employs an adaptive grouping strategy to guide layer grouping based on the topology of DNNs and dynamically adjust the grouping according to the trade-off target. Furthermore, GHCoM considers the fine-grained allocation of computation (i.e., processing elements) and communication (i.e., on-chip bandwidth) resources within each block to mitigate inter-layer resource contention. To jointly optimize layer grouping, block-wise mapping and intra-block resource allocation, GHCoM leverages a two-level genetic algorithm (GA) with tailored encodings and operators that capture the interdependence across the entire design space. Experiments across various workloads and system configurations show that GHCoM consistently outperforms state-of-the-art baselines, achieving 1.08× to 4.79× speedup in execution latency and reducing energy consumption by 1.83% to 87.71%.
{"title":"Adaptive Block-Wise Mapping With Intra-Block Resource Allocation for Multi-DNN Workloads on Heterogeneous Accelerator Systems","authors":"Zhenyu Nie;Haotian Wang;Anthony Theodore Chronopoulos;Zhuo Tang;Kenli Li;Chubo Liu;Zheng Xiao","doi":"10.1109/TPDS.2026.3667207","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3667207","url":null,"abstract":"Deep neural networks (DNNs) dominate workloads on cloud and edge platforms. Meanwhile, the hardware platform towards the heterogeneous system with various accelerators. By mapping layers to their differentpreferred accelerators, the computation cost of each layer can be reduced. While mapping these layers on the same accelerator can reduce the inter-accelerator communication cost. These two costs are often competing and difficult to optimize simultaneously. Therefore, the core challenge in achieving efficient execution of DNN workloads on heterogeneous systems is: how to map layers to achieve the best trade-off between computation and communication costs. Existing works group layers into blocks and perform block-wise mapping to reduce inter-layer communication within blocks. However, when grouping layers, they typically rely on model-agnostic rules, which fail to hide critical inter-layer communication within blocks for diverse DNNs. Moreover, after block mapping, the lack of intra-block resource allocation further increases computation cost of block. In this paper, we propose <italic>GHCoM</i>, a novel block-wise mapping framework for exploring the effective cost trade-offs. <italic>GHCoM</i> employs an adaptive grouping strategy to guide layer grouping based on the topology of DNNs and dynamically adjust the grouping according to the trade-off target. Furthermore, <italic>GHCoM</i> considers the fine-grained allocation of computation (i.e., processing elements) and communication (i.e., on-chip bandwidth) resources within each block to mitigate inter-layer resource contention. To jointly optimize layer grouping, block-wise mapping and intra-block resource allocation, <italic>GHCoM</i> leverages a two-level genetic algorithm (GA) with tailored encodings and operators that capture the interdependence across the entire design space. Experiments across various workloads and system configurations show that <italic>GHCoM</i> consistently outperforms state-of-the-art baselines, achieving 1.08× to 4.79× speedup in execution latency and reducing energy consumption by 1.83% to 87.71%.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"1015-1031"},"PeriodicalIF":6.0,"publicationDate":"2026-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147362433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The growing resource demands of large-scale transformer models pose significant challenges for resource-constrained users, particularly in distributed environments. To address this issue, we propose a federated learning framework called Fed-Grow, which enables multiple participants to collaboratively learn a lightweight scaling operation that transfers knowledge from pretrained small models to a large transformer model. In Fed-Grow, we introduce the Dual-LiGO (Dual Linear Growth Operator) architecture, consisting of Local-LiGO and Global-LiGO components. Local-LiGO addresses model heterogeneity by adapting each participant’s pre-trained model to a common intermediate form, while Global-LiGO facilitates knowledge sharing across participants without sharing local models or raw data, ensuring privacy preservation. This federated approach offers a scalable solution for growing large transformers in a distributed manner, where only the Global-LiGO is shared, significantly reducing communication overhead while maintaining comparable model performance under the same communication constraints. Experimental results demonstrate that Fed-Grow outperforms state-of-the-art methods in terms of accuracy and precision, while reducing the number of trainable parameters by 59.25% and communication costs by 73.01% . These improvements allow for higher efficiency in training large models in distributed environments, without sacrificing performance. To the best of our knowledge, Fed-Grow is the first method that enables cooperative transformer scaling in a distributed setting, making it a practical solution for resource-constrained users.
大型变压器模型日益增长的资源需求对资源受限的用户提出了重大挑战，特别是在分布式环境中。为了解决这个问题，我们提出了一个称为Fed-Grow的联邦学习框架，它使多个参与者能够协作学习轻量级缩放操作，将知识从预训练的小型模型转移到大型变压器模型。在feed - grow中，我们引入了Dual- ligo （Dual Linear Growth Operator）架构，包括Local-LiGO和Global-LiGO组件。local - ligo通过将每个参与者的预训练模型适应为通用的中间形式来解决模型异质性问题，而Global-LiGO促进了参与者之间的知识共享，而无需共享本地模型或原始数据，从而确保了隐私保护。这种联合方法为以分布式方式增长的大型变压器提供了可扩展的解决方案，其中只有Global-LiGO是共享的，在相同的通信约束下显着降低了通信开销，同时保持了可比较的模型性能。实验结果表明，Fed-Grow在准确率和精密度上都优于现有的方法，同时可训练参数的数量减少了59.25%，通信成本减少了73.01%。这些改进允许在不牺牲性能的情况下，在分布式环境中训练大型模型时提高效率。据我们所知，Fed-Grow是第一个在分布式设置中实现变压器协作扩展的方法，使其成为资源受限用户的实用解决方案。
{"title":"Fed-Grow: Federating to Grow Transformers for Resource-Constrained Users Without Model Sharing","authors":"Shikun Shen;Yifei Zou;Yuan Yuan;Hanlin Gu;Peng Li;Xiuzhen Cheng;Falko Dressler;Dongxiao Yu","doi":"10.1109/TPDS.2026.3666309","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3666309","url":null,"abstract":"The growing resource demands of large-scale transformer models pose significant challenges for resource-constrained users, particularly in distributed environments. To address this issue, we propose a federated learning framework called Fed-Grow, which enables multiple participants to collaboratively learn a lightweight scaling operation that transfers knowledge from pretrained small models to a large transformer model. In Fed-Grow, we introduce the Dual-LiGO (Dual Linear Growth Operator) architecture, consisting of Local-LiGO and Global-LiGO components. Local-LiGO addresses model heterogeneity by adapting each participant’s pre-trained model to a common intermediate form, while Global-LiGO facilitates knowledge sharing across participants without sharing local models or raw data, ensuring privacy preservation. This federated approach offers a scalable solution for growing large transformers in a distributed manner, where only the Global-LiGO is shared, significantly reducing communication overhead while maintaining comparable model performance under the same communication constraints. Experimental results demonstrate that Fed-Grow outperforms state-of-the-art methods in terms of accuracy and precision, while reducing the number of trainable parameters by 59.25% and communication costs by 73.01% . These improvements allow for higher efficiency in training large models in distributed environments, without sacrificing performance. To the best of our knowledge, Fed-Grow is the first method that enables cooperative transformer scaling in a distributed setting, making it a practical solution for resource-constrained users.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 5","pages":"1048-1061"},"PeriodicalIF":6.0,"publicationDate":"2026-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147440669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-17DOI: 10.1109/TPDS.2026.3665533
Abhisek Panda;Smruti R. Sarangi
Serverless platforms are widely adopted for deploying applications due to their autoscaling capabilities and pay-as-you-go billing models. These platforms execute an application’s functions inside ephemeral containers and scale the number of containers based on incoming request rates. To meet service level objectives (SLOs), they often over-provision resources by maintaining warm containers or rapidly spawning new ones during traffic bursts. However, this strategy frequently leads to inefficient resource utilization, especially during periods of low activity. Prior research addresses this issue through intelligent scheduling, lightweight virtualization, and container-sharing mechanisms. More recent work aims to improve resource utilization by remodeling the execution of a function within a container to better separate compute and I/O stages. Despite these improvements, existing approaches often introduce delays during execution and induce memory pressure under traffic bursts. In this paper, we present Styx, a novel workflow engine that enhances resource utilization by intelligently decoupling compute and I/O stages. Styx employs a fetch latency predictor that uses real-time system metrics from both the serverless node and the remote storage server to accurately estimate prefetch operations, ensuring input data is available exactly when needed. Furthermore, it offloads the output data upload operation from a container to a host-side data service, thereby efficiently managing provisioned memory. Our approach improves the overall memory allocation by 32.6% when running all the serverless workflows simultaneously when compared to Dataflower + Truffle. Additionally, this method improves the tail latency and the mean latency of a workflow by an average of 26.3% and 21%, respectively.
{"title":"Styx: An Efficient Workflow Engine for Serverless Platforms","authors":"Abhisek Panda;Smruti R. Sarangi","doi":"10.1109/TPDS.2026.3665533","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3665533","url":null,"abstract":"Serverless platforms are widely adopted for deploying applications due to their autoscaling capabilities and pay-as-you-go billing models. These platforms execute an application’s functions inside ephemeral containers and scale the number of containers based on incoming request rates. To meet service level objectives (SLOs), they often over-provision resources by maintaining warm containers or rapidly spawning new ones during traffic bursts. However, this strategy frequently leads to inefficient resource utilization, especially during periods of low activity. Prior research addresses this issue through intelligent scheduling, lightweight virtualization, and container-sharing mechanisms. More recent work aims to improve resource utilization by remodeling the execution of a function within a container to better separate compute and I/O stages. Despite these improvements, existing approaches often introduce delays during execution and induce memory pressure under traffic bursts. In this paper, we present Styx, a novel workflow engine that enhances resource utilization by intelligently decoupling compute and I/O stages. Styx employs a fetch latency predictor that uses real-time system metrics from both the serverless node and the remote storage server to accurately estimate prefetch operations, ensuring input data is available exactly when needed. Furthermore, it offloads the output data upload operation from a container to a host-side data service, thereby efficiently managing provisioned memory. Our approach improves the overall memory allocation by 32.6% when running all the serverless workflows simultaneously when compared to Dataflower + Truffle. Additionally, this method improves the tail latency and the mean latency of a workflow by an average of 26.3% and 21%, respectively.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"982-996"},"PeriodicalIF":6.0,"publicationDate":"2026-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147299679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-12DOI: 10.1109/TPDS.2026.3664114
Jianbin Fang;Kainan Yu;Peng Zhang;Dezun Dong;Xinxin Qi;Xingyu Hou;Ruibo Wang;Kai Lu
The General Matrix Multiplication (GEMM) is a crucial subprogram in high-performance computing (HPC). With the increasing importance of power and energy consumption, modern Digital Signal Processors (DSPs) are being integrated into general-purpose HPC systems. However, due to architecture disparities, traditional optimizations for CPUs and GPUs are not easily applicable to modern DSPs. This paper shares our experience of optimizing the GEMM operation using a CPU-DSP platform as a case study. Our work employs a set of strategies to improve the performance and scalability of GEMM. These strategies focus on developing micro-kernels based on heterogeneous on-chip memory, addressing the memory access bottleneck in multi-core parallelism, and facilitating efficient transpose-GEMM. These approaches, collectively referred to as an efficient and practical library (a.k.a. mtGEMM), maximize computational capabilities and bandwidth utilization of multi-core DSPs, while achieving high performance for variously-shaped GEMMs. Our experimental results demonstrate that mtGEMM can attain between 92% and 96% of the hardware peak, with the multi-core scalability being almost linear.
{"title":"mtGEMM: An Efficient GEMM Library for Modern Multi-Core DSPs","authors":"Jianbin Fang;Kainan Yu;Peng Zhang;Dezun Dong;Xinxin Qi;Xingyu Hou;Ruibo Wang;Kai Lu","doi":"10.1109/TPDS.2026.3664114","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3664114","url":null,"abstract":"The General Matrix Multiplication (GEMM) is a crucial subprogram in high-performance computing (HPC). With the increasing importance of power and energy consumption, modern Digital Signal Processors (DSPs) are being integrated into general-purpose HPC systems. However, due to architecture disparities, traditional optimizations for CPUs and GPUs are not easily applicable to modern DSPs. This paper shares our experience of optimizing the GEMM operation using a CPU-DSP platform as a case study. Our work employs a set of strategies to improve the performance and scalability of GEMM. These strategies focus on developing micro-kernels based on heterogeneous on-chip memory, addressing the memory access bottleneck in multi-core parallelism, and facilitating efficient transpose-GEMM. These approaches, collectively referred to as an efficient and practical library (a.k.a. <sc>mtGEMM</small>), maximize computational capabilities and bandwidth utilization of multi-core DSPs, while achieving high performance for variously-shaped GEMMs. Our experimental results demonstrate that <sc>mtGEMM</small> can attain between 92% and 96% of the hardware peak, with the multi-core scalability being almost linear.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"905-919"},"PeriodicalIF":6.0,"publicationDate":"2026-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-12DOI: 10.1109/TPDS.2026.3664186
Jiangyuan Chen;Xiaohua Xu;Wenfei Wu
"In key-value storage systems, a small number of hot items account for most traffic. Skewed workloads lead to load imbalance among servers, and those holding hotspots become system bottlenecks, degrading overall performance. Recent studies show that load imbalance can be eliminated by deploying a small, fast cache node in front of back-end servers, i.e., in-network cache. Programmable switches enable placing such caches on switches where traffic must pass. Although existing in-network cache schemes effectively balance loads in large-scale storage systems, they perform poorly under write-intensive workloads and lose scalability with growing clients due to imbalanced cache nodes. This paper introduces HarmonyCache, a scalable, high-performance in-network cache system that supports write-back. HarmonyCache employs cache replication and read-write separation: only one cache node handles write requests, while others serve reads only. To achieve scalability and minimize coherence overhead, HarmonyCache proposes an adaptive cache replication scheme to determine where and how many replicas to deploy. In addition, we design heterogeneous in-network caches using different switch resources and propose a hybrid caching scheme. Prototype and extensive experiments show that HarmonyCache significantly improves throughput under various access patterns (read/write-intensive), achieving up to 7.6× throughput gain over state-of-the-art solutions under skewed write-intensive workloads.
{"title":"HarmonyCache: Scalable In-Network Cache With Read-Write Separation","authors":"Jiangyuan Chen;Xiaohua Xu;Wenfei Wu","doi":"10.1109/TPDS.2026.3664186","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3664186","url":null,"abstract":"\"In key-value storage systems, a small number of hot items account for most traffic. Skewed workloads lead to load imbalance among servers, and those holding hotspots become system bottlenecks, degrading overall performance. Recent studies show that load imbalance can be eliminated by deploying a small, fast cache node in front of back-end servers, i.e., in-network cache. Programmable switches enable placing such caches on switches where traffic must pass. Although existing in-network cache schemes effectively balance loads in large-scale storage systems, they perform poorly under write-intensive workloads and lose scalability with growing clients due to imbalanced cache nodes. This paper introduces HarmonyCache, a scalable, high-performance in-network cache system that supports write-back. HarmonyCache employs cache replication and read-write separation: only one cache node handles write requests, while others serve reads only. To achieve scalability and minimize coherence overhead, HarmonyCache proposes an adaptive cache replication scheme to determine where and how many replicas to deploy. In addition, we design heterogeneous in-network caches using different switch resources and propose a hybrid caching scheme. Prototype and extensive experiments show that HarmonyCache significantly improves throughput under various access patterns (read/write-intensive), achieving up to 7.6× throughput gain over state-of-the-art solutions under skewed write-intensive workloads.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"920-933"},"PeriodicalIF":6.0,"publicationDate":"2026-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-06DOI: 10.1109/TPDS.2026.3662253
Yani Liu;Feng Zhang;Yu Zhang;Shuhao Zhang;Bingsheng He;Jianhua Wang;Jidong Zhai;Xiaoyong Du
The exponential increase of stream data in the Big Data era poses critical challenges for SQL queries on compressed streams. These challenges are exacerbated by diverse computational demands and varying application scenarios in stream processing, which lead to increased hardware requirements. Hybrid computing architectures provide a transformative solution in this context by integrating heterogeneous processing units, such as discrete GPUs, CPU-GPU integrated architectures, and edge computing devices to enhance performance. In this paper, we introduce ComStar, a novel compression-aware stream SQL query system that leverages the capabilities of hybrid computing architectures to execute direct queries on compressed stream data without decompression, greatly improving query performance. ComStar incorporates nine lightweight compression algorithms and features an adaptive compression algorithm selector, which optimally chooses the appropriate algorithm based on data characteristics and network conditions. Additionally, ComStar implements a hierarchical multi-tier execution to select the optimal architecture and specific devices for compressed stream SQL queries, enabling fine-grained and efficient execution across the hybrid architecture. Our experiments demonstrate that ComStar achieves an average throughput improvement of 75.6% under 100 Mbps network conditions, leveraging its unique compression-aware query capabilities to outperform contemporary solutions. At a higher network speed of 1 Gbps, ComStar improves throughput by an average of 47.4%. Additionally, ComStar achieves a 28.6% improvement in the throughput/price ratio compared to traditional methods, and a 71.4% enhancement in the throughput/power ratio. Furthermore, the ComStar’s adaptive compression algorithm selector achieves 95.6% accuracy. These results underscore the effectiveness of our system in addressing the challenges posed by the increasing volume of stream data.
{"title":"ComStar: Compression-Aware Stream Query for Heterogeneous Hybrid Architecture","authors":"Yani Liu;Feng Zhang;Yu Zhang;Shuhao Zhang;Bingsheng He;Jianhua Wang;Jidong Zhai;Xiaoyong Du","doi":"10.1109/TPDS.2026.3662253","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3662253","url":null,"abstract":"The exponential increase of stream data in the Big Data era poses critical challenges for SQL queries on compressed streams. These challenges are exacerbated by diverse computational demands and varying application scenarios in stream processing, which lead to increased hardware requirements. Hybrid computing architectures provide a transformative solution in this context by integrating heterogeneous processing units, such as discrete GPUs, CPU-GPU integrated architectures, and edge computing devices to enhance performance. In this paper, we introduce ComStar, a novel compression-aware stream SQL query system that leverages the capabilities of hybrid computing architectures to execute direct queries on compressed stream data without decompression, greatly improving query performance. ComStar incorporates nine lightweight compression algorithms and features an adaptive compression algorithm selector, which optimally chooses the appropriate algorithm based on data characteristics and network conditions. Additionally, ComStar implements a hierarchical multi-tier execution to select the optimal architecture and specific devices for compressed stream SQL queries, enabling fine-grained and efficient execution across the hybrid architecture. Our experiments demonstrate that ComStar achieves an average throughput improvement of 75.6% under 100 Mbps network conditions, leveraging its unique compression-aware query capabilities to outperform contemporary solutions. At a higher network speed of 1 Gbps, ComStar improves throughput by an average of 47.4%. Additionally, ComStar achieves a 28.6% improvement in the throughput/price ratio compared to traditional methods, and a 71.4% enhancement in the throughput/power ratio. Furthermore, the ComStar’s adaptive compression algorithm selector achieves 95.6% accuracy. These results underscore the effectiveness of our system in addressing the challenges posed by the increasing volume of stream data.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"948-965"},"PeriodicalIF":6.0,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147299530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-03DOI: 10.1109/TPDS.2026.3660861
Ran Chen;Huihai An;Zhihua Sa;Ping Gao;Xiaohui Duan;Bertil Schmidt;Yang Yang;Yizhen Chen;Lin Gan;Guangwen Yang;Weiguo Liu
LAMMPS is a widely used molecular dynamics (MD) software package in materials science, computational chemistry, and biophysics, supporting parallel computing from a single CPU core to large supercomputers. The Kunpeng processor features both high memory bandwidth and core density and is therefore an interesting candidate for accelerating compute-intensive workloads. In this article, we target the Kunpeng multi-core architecture and focus on optimizing LAMMPS for modern ARM-based platforms by using the Lennard-Jones (L-J) and Tersoff potentials as representative case studies. We investigate both common and specific optimization challenges, and present a comprehensive performance analysis addressing four key aspects: neighbor list algorithm design, force computation optimization, efficient vectorization, and multi-thread parallelization. Experimental results show that the optimized potentials achieve speedups of approximately $2 times$ and $5 times$, reaching $4.55 times$ and $7.04times$ the performance of the original Intel version for L-J and Tersoff, respectively. Both potentials outperform Intel’s acceleration library, with a peak performance up to $2.9times$$-3.5times$. In terms of parallel efficiency, we evaluate scalability both within a single CPU (small-scale) and across multiple nodes (large-scale). Strong and weak scaling tests within a single CPU show that when the expansion factor is 32 times, parallel efficiency remains above 90%. Large-scale weak scaling across multiple nodes achieves up to 86% efficiency when the expansion factor is 32. Using 32 nodes (18,432 processes), our implementation enables billion-atom simulations with L-J and Tersoff potentials. This work achieves breakthrough performance and provides critical support for large-scale molecular dynamics in engineering applications.
{"title":"Accelerating Molecular Dynamics Simulations on ARM Multi-Core Processors","authors":"Ran Chen;Huihai An;Zhihua Sa;Ping Gao;Xiaohui Duan;Bertil Schmidt;Yang Yang;Yizhen Chen;Lin Gan;Guangwen Yang;Weiguo Liu","doi":"10.1109/TPDS.2026.3660861","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3660861","url":null,"abstract":"LAMMPS is a widely used molecular dynamics (MD) software package in materials science, computational chemistry, and biophysics, supporting parallel computing from a single CPU core to large supercomputers. The Kunpeng processor features both high memory bandwidth and core density and is therefore an interesting candidate for accelerating compute-intensive workloads. In this article, we target the Kunpeng multi-core architecture and focus on optimizing LAMMPS for modern ARM-based platforms by using the Lennard-Jones (L-J) and Tersoff potentials as representative case studies. We investigate both common and specific optimization challenges, and present a comprehensive performance analysis addressing four key aspects: neighbor list algorithm design, force computation optimization, efficient vectorization, and multi-thread parallelization. Experimental results show that the optimized potentials achieve speedups of approximately <inline-formula><tex-math>$2 times$</tex-math></inline-formula> and <inline-formula><tex-math>$5 times$</tex-math></inline-formula>, reaching <inline-formula><tex-math>$4.55 times$</tex-math></inline-formula> and <inline-formula><tex-math>$7.04times$</tex-math></inline-formula> the performance of the original Intel version for L-J and Tersoff, respectively. Both potentials outperform Intel’s acceleration library, with a peak performance up to <inline-formula><tex-math>$2.9times$</tex-math></inline-formula><inline-formula><tex-math>$-3.5times$</tex-math></inline-formula>. In terms of parallel efficiency, we evaluate scalability both within a single CPU (small-scale) and across multiple nodes (large-scale). Strong and weak scaling tests within a single CPU show that when the expansion factor is 32 times, parallel efficiency remains above 90%. Large-scale weak scaling across multiple nodes achieves up to 86% efficiency when the expansion factor is 32. Using 32 nodes (18,432 processes), our implementation enables billion-atom simulations with L-J and Tersoff potentials. This work achieves breakthrough performance and provides critical support for large-scale molecular dynamics in engineering applications.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"805-821"},"PeriodicalIF":6.0,"publicationDate":"2026-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146176021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-03DOI: 10.1109/TPDS.2026.3660379
Muhammad Numan Khan;Young-Koo Lee
Since the emergence of Graph Neural Networks (GNNs), researchers have extensively investigated training on large-scale GNN training because of their success and wide usage in various domains including biological networks, finance, and recommendation systems. This work focuses on training large-scale distributed GNNs, where partitioning massive graphs across multiple machines creates remote communication overhead that becomes a major scalability bottleneck. We introduce a policy-driven caching mechanism that prioritizes node features and embeddings based on access frequency and cross-partition fetch cost, significantly minimizing communication overhead without sacrificing accuracy. Our policies are based on analysis of Node Affinities (NAFs) during multi-hop neighborhood sampling that extend substantially beyond the graph partition boundaries. Analyzing NAFs not only alleviates the communication bottleneck but also provides a systematic mechanism to manage in-memory data effectively, prioritizing GPU storage for node features with high fetch latency. We present FLARE, a system designed to handle partitioned feature data while leveraging the NAF-based caching policy. FLARE substantially reduces both communication overhead and training convergence time. Extensive experiments on benchmark datasets show that training FLARE on a three-layer GCN, GAT, and GraphSAGE across eight GPU machines achieves up to 12.04× (8.12× on average) speedup over DistDGLv2, demonstrating substantial performance gains compared to state-of-the-art methods.
{"title":"FLARE: Efficient Distributed Large-Scale Graph Neural Networks Training With Adaptive Latency-Aware Probabilistic Caching","authors":"Muhammad Numan Khan;Young-Koo Lee","doi":"10.1109/TPDS.2026.3660379","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3660379","url":null,"abstract":"Since the emergence of Graph Neural Networks (GNNs), researchers have extensively investigated training on large-scale GNN training because of their success and wide usage in various domains including biological networks, finance, and recommendation systems. This work focuses on training large-scale distributed GNNs, where partitioning massive graphs across multiple machines creates remote communication overhead that becomes a major scalability bottleneck. We introduce a policy-driven caching mechanism that prioritizes node features and embeddings based on access frequency and cross-partition fetch cost, significantly minimizing communication overhead without sacrificing accuracy. Our policies are based on analysis of Node Affinities (NAFs) during multi-hop neighborhood sampling that extend substantially beyond the graph partition boundaries. Analyzing NAFs not only alleviates the communication bottleneck but also provides a systematic mechanism to manage in-memory data effectively, prioritizing GPU storage for node features with high fetch latency. We present FLARE, a system designed to handle partitioned feature data while leveraging the NAF-based caching policy. FLARE substantially reduces both communication overhead and training convergence time. Extensive experiments on benchmark datasets show that training FLARE on a three-layer GCN, GAT, and GraphSAGE across eight GPU machines achieves up to 12.04× (8.12× on average) speedup over DistDGLv2, demonstrating substantial performance gains compared to state-of-the-art methods.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"849-866"},"PeriodicalIF":6.0,"publicationDate":"2026-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146176023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Inter-FPGA communication bandwidth has become a limiting factor in scaling memory-intensive workloads on FPGA-based systems. While modern FPGAs integrate high-bandwidth memory (HBM) to increase local memory throughput, network interfaces often lag behind, creating an imbalance between computation and communication resources. Data compression is a technique to increase effective communication bandwidth by reducing the amount of data transferred, but existing solutions struggle to meet the performance and operation latency requirements of FPGA-based platforms. This paper presents a high-throughput lossy compression framework that enables sub-microsecond latency communication in FPGA clusters. The proposed design addresses the challenge of aligning variable-length compressed data with fixed-width network channels by using transpose circuits, memory-bank reordering, and word-wise operations. A run-length encoding scheme with bounded error is employed to compress floating-point and fixed-point data without relying on complex fine-grained bit-level manipulations, enabling low-latency and scalable implementation. The proposed architecture is implemented on a custom Stratix 10 MX2100 FPGA card equipped with eight 50 Gbps network ports and silicon photonics transceivers. The system achieves up to 757 Gbps of aggregate bandwidth per FPGA in collective communication operations. Compression and decompression are performed within 590 ns total latency, while maintaining the quality of results in a GradAllReduce workload for deep learning.
{"title":"A 590-Nanosecond 757-Gbps FPGA Lossy Compressed Network","authors":"Michihiro Koibuchi;Takumi Honda;Naoto Fukumoto;Shoichi Hirasawa;Koji Nakano","doi":"10.1109/TPDS.2026.3659817","DOIUrl":"https://doi.org/10.1109/TPDS.2026.3659817","url":null,"abstract":"Inter-FPGA communication bandwidth has become a limiting factor in scaling memory-intensive workloads on FPGA-based systems. While modern FPGAs integrate high-bandwidth memory (HBM) to increase local memory throughput, network interfaces often lag behind, creating an imbalance between computation and communication resources. Data compression is a technique to increase effective communication bandwidth by reducing the amount of data transferred, but existing solutions struggle to meet the performance and operation latency requirements of FPGA-based platforms. This paper presents a high-throughput lossy compression framework that enables sub-microsecond latency communication in FPGA clusters. The proposed design addresses the challenge of aligning variable-length compressed data with fixed-width network channels by using transpose circuits, memory-bank reordering, and word-wise operations. A run-length encoding scheme with bounded error is employed to compress floating-point and fixed-point data without relying on complex fine-grained bit-level manipulations, enabling low-latency and scalable implementation. The proposed architecture is implemented on a custom Stratix 10 MX2100 FPGA card equipped with eight 50 Gbps network ports and silicon photonics transceivers. The system achieves up to 757 Gbps of aggregate bandwidth per FPGA in collective communication operations. Compression and decompression are performed within 590 ns total latency, while maintaining the quality of results in a GradAllReduce workload for deep learning.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 4","pages":"836-848"},"PeriodicalIF":6.0,"publicationDate":"2026-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11370288","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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