利用差分斜坡的两步式单斜坡 ADC，适用于 CMOS 图像传感器

IF 1.8 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Circuits, Systems and Signal Processing Pub Date : 2024-07-18 DOI:10.1007/s00034-024-02767-2

Dongxing Fang, Kaiming Nie, Ziyang Zhang, Jiangtao Xu

{"title":"利用差分斜坡的两步式单斜坡 ADC，适用于 CMOS 图像传感器","authors":"Dongxing Fang, Kaiming Nie, Ziyang Zhang, Jiangtao Xu","doi":"10.1007/s00034-024-02767-2","DOIUrl":null,"url":null,"abstract":"<p>This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 µs. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"15 1","pages":""},"PeriodicalIF":1.8000,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Two-Step Single-Slope ADC Utilizing Differential Ramps for CMOS Image Sensors\",\"authors\":\"Dongxing Fang, Kaiming Nie, Ziyang Zhang, Jiangtao Xu\",\"doi\":\"10.1007/s00034-024-02767-2\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 µs. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.</p>\",\"PeriodicalId\":10227,\"journal\":{\"name\":\"Circuits, Systems and Signal Processing\",\"volume\":\"15 1\",\"pages\":\"\"},\"PeriodicalIF\":1.8000,\"publicationDate\":\"2024-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Circuits, Systems and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1007/s00034-024-02767-2\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Circuits, Systems and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1007/s00034-024-02767-2","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种用于 CMOS 图像传感器（CIS）的两步单斜率（TS-SS）模数转换器（ADC）。所提出的 TS-SS ADC 利用预比较器将像素信号分为小信号区和大信号区。在量化大像素信号时，TS-SS ADC 进入加速模式，利用斜坡发生器的差分拓扑结构加快量化速度。加速模式缩短了行周期，使 320 MHz 时钟下的行周期从 27.3 µs 缩短到 18.75 µs，缩短了 31.3%。所设计的 12 位 TS-SS ADC 采用 110 nm 1P4M CMOS 技术设计，其线性度通过工艺拐角后仿真和蒙特卡罗仿真进行了验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

摘要图片

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Two-Step Single-Slope ADC Utilizing Differential Ramps for CMOS Image Sensors

This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 µs. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Circuits, Systems and Signal Processing 工程技术-工程：电子与电气

CiteScore

4.80

自引率

13.00%

发文量

321

审稿时长

4.6 months

期刊介绍： Rapid developments in the analog and digital processing of signals for communication, control, and computer systems have made the theory of electrical circuits and signal processing a burgeoning area of research and design. The aim of Circuits, Systems, and Signal Processing (CSSP) is to help meet the needs of outlets for significant research papers and state-of-the-art review articles in the area. The scope of the journal is broad, ranging from mathematical foundations to practical engineering design. It encompasses, but is not limited to, such topics as linear and nonlinear networks, distributed circuits and systems, multi-dimensional signals and systems, analog filters and signal processing, digital filters and signal processing, statistical signal processing, multimedia, computer aided design, graph theory, neural systems, communication circuits and systems, and VLSI signal processing. The Editorial Board is international, and papers are welcome from throughout the world. The journal is devoted primarily to research papers, but survey, expository, and tutorial papers are also published. Circuits, Systems, and Signal Processing (CSSP) is published twelve times annually.