{"title":"通过高效冗余策略实现 < 6× 10-9 比特错误率的 266F2 超稳定差分 NOR 结构物理不可克隆函数","authors":"Haoyi Zhang;Jiahao Song;Haoyang Luo;Xiyuan Tang;Yuan Wang;Runsheng Wang;Ru Huang","doi":"10.1109/TCSII.2024.3433543","DOIUrl":null,"url":null,"abstract":"This brief presents a NOR-structured physically unclonable function (PUF) tailored for low-cost Internet of Things (IoT) applications. The proposed NOR-structured PUF utilizes a single minimum-sized differential NMOS pair, capitalizing on threshold-voltage mismatch as the entropy source. Fabricated in 65nm CMOS, the basic PUF cell is a \n<inline-formula> <tex-math>$58F^{2}$ </tex-math></inline-formula>\n differential NMOS pair, demonstrating a raw bit error rate (BER) of 0.31%. To further enhance the stability and achieve an ultra-low BER, we introduce an area-efficient redundancy strategy. By incorporating 4x redundancy cells (\n<inline-formula> <tex-math>$266F^{2}$ </tex-math></inline-formula>\n in total), the prototype chip achieves an ultra-low BER (zero error in 20M bits), over a wide temperature range (−20 to 125°C) and supply voltage variations (0.8 to 1.2V). The core energy consumption is only 63fJ/bit, offering a low-cost and highly stable solution for IoT applications.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4979-4983"},"PeriodicalIF":4.0000,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6×10-9 Bit Error Rate Through Efficient Redundancy Strategy\",\"authors\":\"Haoyi Zhang;Jiahao Song;Haoyang Luo;Xiyuan Tang;Yuan Wang;Runsheng Wang;Ru Huang\",\"doi\":\"10.1109/TCSII.2024.3433543\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents a NOR-structured physically unclonable function (PUF) tailored for low-cost Internet of Things (IoT) applications. The proposed NOR-structured PUF utilizes a single minimum-sized differential NMOS pair, capitalizing on threshold-voltage mismatch as the entropy source. Fabricated in 65nm CMOS, the basic PUF cell is a \\n<inline-formula> <tex-math>$58F^{2}$ </tex-math></inline-formula>\\n differential NMOS pair, demonstrating a raw bit error rate (BER) of 0.31%. To further enhance the stability and achieve an ultra-low BER, we introduce an area-efficient redundancy strategy. By incorporating 4x redundancy cells (\\n<inline-formula> <tex-math>$266F^{2}$ </tex-math></inline-formula>\\n in total), the prototype chip achieves an ultra-low BER (zero error in 20M bits), over a wide temperature range (−20 to 125°C) and supply voltage variations (0.8 to 1.2V). The core energy consumption is only 63fJ/bit, offering a low-cost and highly stable solution for IoT applications.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"71 12\",\"pages\":\"4979-4983\"},\"PeriodicalIF\":4.0000,\"publicationDate\":\"2024-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10609250/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10609250/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6×10-9 Bit Error Rate Through Efficient Redundancy Strategy
This brief presents a NOR-structured physically unclonable function (PUF) tailored for low-cost Internet of Things (IoT) applications. The proposed NOR-structured PUF utilizes a single minimum-sized differential NMOS pair, capitalizing on threshold-voltage mismatch as the entropy source. Fabricated in 65nm CMOS, the basic PUF cell is a
$58F^{2}$
differential NMOS pair, demonstrating a raw bit error rate (BER) of 0.31%. To further enhance the stability and achieve an ultra-low BER, we introduce an area-efficient redundancy strategy. By incorporating 4x redundancy cells (
$266F^{2}$
in total), the prototype chip achieves an ultra-low BER (zero error in 20M bits), over a wide temperature range (−20 to 125°C) and supply voltage variations (0.8 to 1.2V). The core energy consumption is only 63fJ/bit, offering a low-cost and highly stable solution for IoT applications.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.