Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Junjie Li;Zhengyang Li
{"title":"用于移动卫星通信 (SOTM) 的 K 波段 4 通道相控阵接收器 IC,相位误差均方根值为 0.78°-1.22°,增益误差均方根值为 0.14-0.32 dB","authors":"Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Junjie Li;Zhengyang Li","doi":"10.1109/TCSII.2024.3432528","DOIUrl":null,"url":null,"abstract":"This brief presents a high accuracy high linearity K-band 4-channel phased array receiver for satellite communication (SATCOM). Structural improvement and parameter optimization have been carried out to enhance the phase and gain control precision. The presented receiver employs a novel \n<inline-formula> <tex-math>$L-C$ </tex-math></inline-formula>\n compensation and variable resistance technique in the quadrature all-pass filter (QAF) for phase shifter (PS) to reduce the phase error. Neutralization capacitance and redundancy control bit are adopted in the attenuator (ATT) to reduce the gain error. A 3-stage low noise amplifier (LNA) has been optimized to provide high gain, high input-referred 1-dB gain compression point and low noise. The receiver achieves a 360° phase shifting range with a 6-bit resolution and a 31.5 dB attenuation range with 0.5 dB step. The measured root mean square (RMS) phase error and gain error are 0.78° – 1.22° and 0.14–0.32 dB, respectively, over the frequency of 17 GHz to 23 GHz. Each channel achieves a measured gain of 23 dB, an input-referred 1-dB gain compression point (IP1dB) of −29.8 dBm at the maximum gain, and a low noise figure (NF) of 3.4–3.9 dB. The 4-channel receiver is implemented in 40-nm CMOS process and occupies a chip area of 3.85 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"4869-4873"},"PeriodicalIF":4.0000,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"0.78–1.22° RMS Phase Error, 0.14–0.32 dB RMS Gain Error, K-Band 4-Channel Phased Array Receiver IC for Satcom on the Move (SOTM)\",\"authors\":\"Youming Zhang;Fengyi Huang;Xusheng Tang;Zhennan Wei;Yunqi Cao;Junjie Li;Zhengyang Li\",\"doi\":\"10.1109/TCSII.2024.3432528\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This brief presents a high accuracy high linearity K-band 4-channel phased array receiver for satellite communication (SATCOM). Structural improvement and parameter optimization have been carried out to enhance the phase and gain control precision. The presented receiver employs a novel \\n<inline-formula> <tex-math>$L-C$ </tex-math></inline-formula>\\n compensation and variable resistance technique in the quadrature all-pass filter (QAF) for phase shifter (PS) to reduce the phase error. Neutralization capacitance and redundancy control bit are adopted in the attenuator (ATT) to reduce the gain error. A 3-stage low noise amplifier (LNA) has been optimized to provide high gain, high input-referred 1-dB gain compression point and low noise. The receiver achieves a 360° phase shifting range with a 6-bit resolution and a 31.5 dB attenuation range with 0.5 dB step. The measured root mean square (RMS) phase error and gain error are 0.78° – 1.22° and 0.14–0.32 dB, respectively, over the frequency of 17 GHz to 23 GHz. Each channel achieves a measured gain of 23 dB, an input-referred 1-dB gain compression point (IP1dB) of −29.8 dBm at the maximum gain, and a low noise figure (NF) of 3.4–3.9 dB. The 4-channel receiver is implemented in 40-nm CMOS process and occupies a chip area of 3.85 mm2.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"71 12\",\"pages\":\"4869-4873\"},\"PeriodicalIF\":4.0000,\"publicationDate\":\"2024-07-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10606435/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10606435/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
0.78–1.22° RMS Phase Error, 0.14–0.32 dB RMS Gain Error, K-Band 4-Channel Phased Array Receiver IC for Satcom on the Move (SOTM)
This brief presents a high accuracy high linearity K-band 4-channel phased array receiver for satellite communication (SATCOM). Structural improvement and parameter optimization have been carried out to enhance the phase and gain control precision. The presented receiver employs a novel
$L-C$
compensation and variable resistance technique in the quadrature all-pass filter (QAF) for phase shifter (PS) to reduce the phase error. Neutralization capacitance and redundancy control bit are adopted in the attenuator (ATT) to reduce the gain error. A 3-stage low noise amplifier (LNA) has been optimized to provide high gain, high input-referred 1-dB gain compression point and low noise. The receiver achieves a 360° phase shifting range with a 6-bit resolution and a 31.5 dB attenuation range with 0.5 dB step. The measured root mean square (RMS) phase error and gain error are 0.78° – 1.22° and 0.14–0.32 dB, respectively, over the frequency of 17 GHz to 23 GHz. Each channel achieves a measured gain of 23 dB, an input-referred 1-dB gain compression point (IP1dB) of −29.8 dBm at the maximum gain, and a low noise figure (NF) of 3.4–3.9 dB. The 4-channel receiver is implemented in 40-nm CMOS process and occupies a chip area of 3.85 mm2.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.