Youming Zhang;Xusheng Tang;Tonglu Jiao;Peng Liu;Jingchen Liu
{"title":"利用频率相关隐含电容中和技术设计具有超低 $K_{\\text{VCO}}$ 的倍频程调谐范围 $LC$ VCO","authors":"Youming Zhang;Xusheng Tang;Tonglu Jiao;Peng Liu;Jingchen Liu","doi":"10.1109/TVLSI.2024.3430544","DOIUrl":null,"url":null,"abstract":"This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain (\n<inline-formula> <tex-math>$K_{\\text {VCO}}$ </tex-math></inline-formula>\n) across an octave frequency tuning range (TR). Series interconnect inductors are used between capacitor units to feature the inverse capacitance-frequency (C–f) relationship with varactors, thus yielding the proposed FD-ICN. A split 8-bit capacitor bank with centrosymmetric double-cross layout pattern is designed, enabling an enhanced FD-ICN through multiple capacitance equivalent iterations of the capacitor bank. The proposed FD-ICN technique is validated in a prototype of dual-mode electric-coupling VCO and fabricated in 130-nm CMOS process, exhibiting a measured frequency TR of 72.1% from 6.49 to 13.81 GHz with a \n<inline-formula> <tex-math>$K_{\\text {VCO}}$ </tex-math></inline-formula>\n of 7–73 MHz/V. The VCO shows a competitive phase noise (PN) and figures-of-merit in TR (FoM\n<inline-formula> <tex-math>$\\rm {_{T}}$ </tex-math></inline-formula>\n) from −121.3 to −111.4 dBc/Hz and 197.4 to 201.7 dBc/Hz at 1-MHz offset across the whole TR.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Octave Tuning Range LC VCO With Ultralow KVCO Using Frequency-Dependent Implicit Capacitance Neutralization Technique\",\"authors\":\"Youming Zhang;Xusheng Tang;Tonglu Jiao;Peng Liu;Jingchen Liu\",\"doi\":\"10.1109/TVLSI.2024.3430544\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain (\\n<inline-formula> <tex-math>$K_{\\\\text {VCO}}$ </tex-math></inline-formula>\\n) across an octave frequency tuning range (TR). Series interconnect inductors are used between capacitor units to feature the inverse capacitance-frequency (C–f) relationship with varactors, thus yielding the proposed FD-ICN. A split 8-bit capacitor bank with centrosymmetric double-cross layout pattern is designed, enabling an enhanced FD-ICN through multiple capacitance equivalent iterations of the capacitor bank. The proposed FD-ICN technique is validated in a prototype of dual-mode electric-coupling VCO and fabricated in 130-nm CMOS process, exhibiting a measured frequency TR of 72.1% from 6.49 to 13.81 GHz with a \\n<inline-formula> <tex-math>$K_{\\\\text {VCO}}$ </tex-math></inline-formula>\\n of 7–73 MHz/V. The VCO shows a competitive phase noise (PN) and figures-of-merit in TR (FoM\\n<inline-formula> <tex-math>$\\\\rm {_{T}}$ </tex-math></inline-formula>\\n) from −121.3 to −111.4 dBc/Hz and 197.4 to 201.7 dBc/Hz at 1-MHz offset across the whole TR.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10609832/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10609832/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Design of Octave Tuning Range LC VCO With Ultralow KVCO Using Frequency-Dependent Implicit Capacitance Neutralization Technique
This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain (
$K_{\text {VCO}}$
) across an octave frequency tuning range (TR). Series interconnect inductors are used between capacitor units to feature the inverse capacitance-frequency (C–f) relationship with varactors, thus yielding the proposed FD-ICN. A split 8-bit capacitor bank with centrosymmetric double-cross layout pattern is designed, enabling an enhanced FD-ICN through multiple capacitance equivalent iterations of the capacitor bank. The proposed FD-ICN technique is validated in a prototype of dual-mode electric-coupling VCO and fabricated in 130-nm CMOS process, exhibiting a measured frequency TR of 72.1% from 6.49 to 13.81 GHz with a
$K_{\text {VCO}}$
of 7–73 MHz/V. The VCO shows a competitive phase noise (PN) and figures-of-merit in TR (FoM
$\rm {_{T}}$
) from −121.3 to −111.4 dBc/Hz and 197.4 to 201.7 dBc/Hz at 1-MHz offset across the whole TR.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.