Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange

In this brief, a low-latency hardware architecture is presented for the peak-to-average power ratio (PAPR) reduction in discrete multitone (DMT) systems. The state-of-the-art scheme suffers from high latency due to a series of selections in calculating the midrange of the DMT frame. To overcome the drawback, an approximate calculation of the midrange that transforms the dominant operation from the selections to the summation is proposed. Grounded on the transformation, in addition, a low-latency architecture to calculate the approximate midrange is constituted. While the selections involve negation, carry propagation, and multiplexing in every stage, the summation can be promptly done by carry-save adders (CSAs) without such manipulations. Slightly relaxing the accuracy of the midrange, as a result, the overall latency can be effectively alleviated compared with the state-of-the-art counterpart.