{"title":"具有字行写入辅助功能和内置读缓冲器方案的数据依赖性半选择自由 GSRAM 单元,可用于基于 PUFs 的物联网设备","authors":"","doi":"10.1016/j.aeue.2024.155448","DOIUrl":null,"url":null,"abstract":"<div><p>In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-V<sub>th</sub> techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.</p><p>At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR<sup>2</sup>, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.</p><p>Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.</p></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":null,"pages":null},"PeriodicalIF":3.0000,"publicationDate":"2024-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices\",\"authors\":\"\",\"doi\":\"10.1016/j.aeue.2024.155448\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-V<sub>th</sub> techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.</p><p>At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR<sup>2</sup>, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.</p><p>Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.</p></div>\",\"PeriodicalId\":50844,\"journal\":{\"name\":\"Aeu-International Journal of Electronics and Communications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":3.0000,\"publicationDate\":\"2024-07-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Aeu-International Journal of Electronics and Communications\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1434841124003340\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Aeu-International Journal of Electronics and Communications","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1434841124003340","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices
In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-Vth techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.
At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.
Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.
期刊介绍:
AEÜ is an international scientific journal which publishes both original works and invited tutorials. The journal''s scope covers all aspects of theory and design of circuits, systems and devices for electronics, signal processing, and communication, including:
signal and system theory, digital signal processing
network theory and circuit design
information theory, communication theory and techniques, modulation, source and channel coding
switching theory and techniques, communication protocols
optical communications
microwave theory and techniques, radar, sonar
antennas, wave propagation
AEÜ publishes full papers and letters with very short turn around time but a high standard review process. Review cycles are typically finished within twelve weeks by application of modern electronic communication facilities.