Adaptive prairie dog optimization based variable length conditional counter for designing multiplier

Binary counters (BC) are electronic devices that are used for counting the particular events that have been happened, followed by storing and displaying the count numbers. BC includes clock signal with sequential logic circuit for the effectuation of counting operation. It is used in many applications like FM decoders to memory chips. In this work we designed a serial multiplier using the proposed Adaptive Prairie Dog optimization (APDO) based variable length conditional counter (VLCC) for the mitigation delay. The suggested work is motivated by the need for an efficient multiplier design to mitigate delay. Mitigating delay in multiplier design is essential for various reasons, particularly in the fields of digital signal processing, computer arithmetic, and high-performance computing. The proposed technique is used to design the multiplier with reduced path delay and enhances the slack interval with various frequencies. The maximized frequency operation is evaluated with the slack interval of the circuit. Simulations are made using Mentor Graphics EDA simulator tool and analyzed the slack time and compared with state-of-art works. The implementation of 8-bit binary multiplier is effectuated in CMOS technology. Our proposed design surpasses all the other design in terms of mitigated computational delay and enhanced slack time. At higher frequency, the proposed method offers improved slack time of 14 % and 68 % of multiplier circuit to reduce delay. Due to the simulation investigations, 18 % slack time improved and reduce 87 % to the critical path delay when compare 45 nm with the 350-nm CMOS technology.