Insights on Asymmetrical Electrode Geometric Effect to Enhance Gate-Drain-Bias Stability of Vertical-Channel InGaZnO Thin-Film Transistor

The asymmetrical gate-drain bias stress (GDBS) stability of a mesa-shaped vertical-channel thin-film transistors (VTFTs) was investigated using an In-Ga-Zn–O (IGZO) active layer prepared by atomic-layer deposition. The GDBS measurements were conducted with variations in electrode configurations and overlapped areas between the active and bottom electrode regions. The GDBS stability of the IGZO VTFTs was found to be significantly degraded, when a plasma-damaged electrode was used as the drain electrode, due to the formation of defective channel regions that are more susceptible to the hot carrier effect. To address the effect of plasma-damaged electrode, an ultrathin passivation layer was introduced, resulting in the achievement of VTFTs with excellent and uniform GDBS stability.

Graphical Abstract