{"title":"用于多模生物信号采集的八通道系统级封装中的 370-nW Bio-AFE,输入噪声为 2.9 美元/毫微伏","authors":"Patrick Fath;Harald Pretl","doi":"10.1109/TVLSI.2024.3430059","DOIUrl":null,"url":null,"abstract":"A fully integrated and reconfigurable octa-channel bio-signal acquisition system-in-package (SiP), which enables the wireless measurement of electromyography (EMG), electrocardiogram (ECG), or electroencephalography (EEG), is presented in this article. Each chiplet contains an analog front end in combination with a channel-selection multiplexer, a successive-approximation-register analog-digital converter (SAR-ADC), an ultra-wideband transmitter (UWB-TX), a low-power on-chip crystal-based clock generation circuit, and a low-dropout voltage regulator, including voltage reference. The die occupies an area of 3.64mm2 in a 180-nm 1P6M CMOS technology. A flexible acquisition of bio-potentials is possible due to the rail-to-rail (R-R) input dc tolerance and multiple bandwidth and gain modes (0.2–128/512/2048Hz, and 19.9–53.1dB, respectively). In addition, a low total harmonic distortion (THD) of −51.1dB of the bio-signal acquisition analog front end (Bio-AFE) for bio-signal relevant levels and a high signal-to-noise-and-distortion ratio (SNDR) of 83.0dB of the SAR-ADC result in a high linearity of the recorded bio-signals. A low input-referred noise ranging from 2.9 to 7.1\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\nVrms, together with a high differential input impedance of 216M\n<inline-formula> <tex-math>$\\Omega $ </tex-math></inline-formula>\n and a common-mode rejection ratio (CMRR) of 81.6dB, is essential for the acquisition of the low-amplitude bio-signals. The low-power consumption of 0.37–1\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\nW per channel (mode-dependent) of the Bio-AFE and that of 1.22\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\nW per channel of the SAR-ADC, both from a 1-V supply, enable battery- or RF-powered applications in a small form factor.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 12","pages":"2173-2185"},"PeriodicalIF":2.8000,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612998","citationCount":"0","resultStr":"{\"title\":\"A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition\",\"authors\":\"Patrick Fath;Harald Pretl\",\"doi\":\"10.1109/TVLSI.2024.3430059\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully integrated and reconfigurable octa-channel bio-signal acquisition system-in-package (SiP), which enables the wireless measurement of electromyography (EMG), electrocardiogram (ECG), or electroencephalography (EEG), is presented in this article. Each chiplet contains an analog front end in combination with a channel-selection multiplexer, a successive-approximation-register analog-digital converter (SAR-ADC), an ultra-wideband transmitter (UWB-TX), a low-power on-chip crystal-based clock generation circuit, and a low-dropout voltage regulator, including voltage reference. The die occupies an area of 3.64mm2 in a 180-nm 1P6M CMOS technology. A flexible acquisition of bio-potentials is possible due to the rail-to-rail (R-R) input dc tolerance and multiple bandwidth and gain modes (0.2–128/512/2048Hz, and 19.9–53.1dB, respectively). In addition, a low total harmonic distortion (THD) of −51.1dB of the bio-signal acquisition analog front end (Bio-AFE) for bio-signal relevant levels and a high signal-to-noise-and-distortion ratio (SNDR) of 83.0dB of the SAR-ADC result in a high linearity of the recorded bio-signals. A low input-referred noise ranging from 2.9 to 7.1\\n<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>\\nVrms, together with a high differential input impedance of 216M\\n<inline-formula> <tex-math>$\\\\Omega $ </tex-math></inline-formula>\\n and a common-mode rejection ratio (CMRR) of 81.6dB, is essential for the acquisition of the low-amplitude bio-signals. The low-power consumption of 0.37–1\\n<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>\\nW per channel (mode-dependent) of the Bio-AFE and that of 1.22\\n<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>\\nW per channel of the SAR-ADC, both from a 1-V supply, enable battery- or RF-powered applications in a small form factor.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"32 12\",\"pages\":\"2173-2185\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-07-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612998\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10612998/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10612998/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition
A fully integrated and reconfigurable octa-channel bio-signal acquisition system-in-package (SiP), which enables the wireless measurement of electromyography (EMG), electrocardiogram (ECG), or electroencephalography (EEG), is presented in this article. Each chiplet contains an analog front end in combination with a channel-selection multiplexer, a successive-approximation-register analog-digital converter (SAR-ADC), an ultra-wideband transmitter (UWB-TX), a low-power on-chip crystal-based clock generation circuit, and a low-dropout voltage regulator, including voltage reference. The die occupies an area of 3.64mm2 in a 180-nm 1P6M CMOS technology. A flexible acquisition of bio-potentials is possible due to the rail-to-rail (R-R) input dc tolerance and multiple bandwidth and gain modes (0.2–128/512/2048Hz, and 19.9–53.1dB, respectively). In addition, a low total harmonic distortion (THD) of −51.1dB of the bio-signal acquisition analog front end (Bio-AFE) for bio-signal relevant levels and a high signal-to-noise-and-distortion ratio (SNDR) of 83.0dB of the SAR-ADC result in a high linearity of the recorded bio-signals. A low input-referred noise ranging from 2.9 to 7.1
$\mu $
Vrms, together with a high differential input impedance of 216M
$\Omega $
and a common-mode rejection ratio (CMRR) of 81.6dB, is essential for the acquisition of the low-amplitude bio-signals. The low-power consumption of 0.37–1
$\mu $
W per channel (mode-dependent) of the Bio-AFE and that of 1.22
$\mu $
W per channel of the SAR-ADC, both from a 1-V supply, enable battery- or RF-powered applications in a small form factor.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.