{"title":"用于低功耗嵌入式应用的基于带对带隧道技术的统一 RAM (URAM)","authors":"Avinash Lahgere;Alok Kumar Kamal;Rishu Kumar","doi":"10.1109/TNANO.2024.3436014","DOIUrl":null,"url":null,"abstract":"In this article, we have reported a tunnel field-effect transistor (TFET) based unified random access memory (T-URAM), integrating nonvolatile memory (NVM) and single transistor (1T) DRAM into a single TFET device. Unlike previously published URAMs, the proposed T-URAM utilizes band-to-band tunneling (BTBT) conduction for programming both NVM and 1T DRAM. This approach offers two main advantages: low supply voltage requirements and disturbance-free NVM operation. Additionally, T-URAM ensures interference-free memory operation through separate gates for NVM and 1T DRAM. Simulations show that T-URAM requires 1.5× to 4.5× less supply voltage compared to existing URAMs. At 358 K, the retention time (RT) of T-URAM in 1T DRAM mode is 500 ms, which is \n<inline-formula><tex-math>$\\sim$</tex-math></inline-formula>\n 62.5× and \n<inline-formula><tex-math>$\\sim$</tex-math></inline-formula>\n 7.8× higher than the buried n-well bulk FinFET URAM and ITRS prediction, respectively. For NVM mode, the RT at a gate length of 50 nm matches that of previously reported URAMs. The sense margin of T-URAM in 1T DRAM mode at 358 K is about 1.9 \n<inline-formula><tex-math>$\\mu$</tex-math></inline-formula>\nA/\n<inline-formula><tex-math>$\\mu$</tex-math></inline-formula>\nm, which is roughly 7.6× higher than TFT-based URAM. We also propose a 2x2 crossbar memory array implementation using T-URAM. These findings pave the way for designing low-power, multi-purpose embedded memory for future applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"629-635"},"PeriodicalIF":2.1000,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Band-to-Band Tunneling Based Unified RAM (URAM) for Low Power Embedded Applications\",\"authors\":\"Avinash Lahgere;Alok Kumar Kamal;Rishu Kumar\",\"doi\":\"10.1109/TNANO.2024.3436014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this article, we have reported a tunnel field-effect transistor (TFET) based unified random access memory (T-URAM), integrating nonvolatile memory (NVM) and single transistor (1T) DRAM into a single TFET device. Unlike previously published URAMs, the proposed T-URAM utilizes band-to-band tunneling (BTBT) conduction for programming both NVM and 1T DRAM. This approach offers two main advantages: low supply voltage requirements and disturbance-free NVM operation. Additionally, T-URAM ensures interference-free memory operation through separate gates for NVM and 1T DRAM. Simulations show that T-URAM requires 1.5× to 4.5× less supply voltage compared to existing URAMs. At 358 K, the retention time (RT) of T-URAM in 1T DRAM mode is 500 ms, which is \\n<inline-formula><tex-math>$\\\\sim$</tex-math></inline-formula>\\n 62.5× and \\n<inline-formula><tex-math>$\\\\sim$</tex-math></inline-formula>\\n 7.8× higher than the buried n-well bulk FinFET URAM and ITRS prediction, respectively. For NVM mode, the RT at a gate length of 50 nm matches that of previously reported URAMs. The sense margin of T-URAM in 1T DRAM mode at 358 K is about 1.9 \\n<inline-formula><tex-math>$\\\\mu$</tex-math></inline-formula>\\nA/\\n<inline-formula><tex-math>$\\\\mu$</tex-math></inline-formula>\\nm, which is roughly 7.6× higher than TFT-based URAM. We also propose a 2x2 crossbar memory array implementation using T-URAM. These findings pave the way for designing low-power, multi-purpose embedded memory for future applications.\",\"PeriodicalId\":449,\"journal\":{\"name\":\"IEEE Transactions on Nanotechnology\",\"volume\":\"23 \",\"pages\":\"629-635\"},\"PeriodicalIF\":2.1000,\"publicationDate\":\"2024-07-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Nanotechnology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10616238/\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Nanotechnology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10616238/","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Band-to-Band Tunneling Based Unified RAM (URAM) for Low Power Embedded Applications
In this article, we have reported a tunnel field-effect transistor (TFET) based unified random access memory (T-URAM), integrating nonvolatile memory (NVM) and single transistor (1T) DRAM into a single TFET device. Unlike previously published URAMs, the proposed T-URAM utilizes band-to-band tunneling (BTBT) conduction for programming both NVM and 1T DRAM. This approach offers two main advantages: low supply voltage requirements and disturbance-free NVM operation. Additionally, T-URAM ensures interference-free memory operation through separate gates for NVM and 1T DRAM. Simulations show that T-URAM requires 1.5× to 4.5× less supply voltage compared to existing URAMs. At 358 K, the retention time (RT) of T-URAM in 1T DRAM mode is 500 ms, which is
$\sim$
62.5× and
$\sim$
7.8× higher than the buried n-well bulk FinFET URAM and ITRS prediction, respectively. For NVM mode, the RT at a gate length of 50 nm matches that of previously reported URAMs. The sense margin of T-URAM in 1T DRAM mode at 358 K is about 1.9
$\mu$
A/
$\mu$
m, which is roughly 7.6× higher than TFT-based URAM. We also propose a 2x2 crossbar memory array implementation using T-URAM. These findings pave the way for designing low-power, multi-purpose embedded memory for future applications.
期刊介绍:
The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.