{"title":"BiNPU:33.0 MOP/s/LUT 二进制神经网络推理处理器,在 28 nm FPGA 中实现 88.26% 的 CIFAR10 精确度和 1.9 Mbit 片上参数","authors":"Gil-Ho Kwak;Tae-Hwan Kim","doi":"10.1109/TCSII.2024.3440965","DOIUrl":null,"url":null,"abstract":"An efficient processor to perform inference of binary neural networks (BNNs) is presented. The proposed processor, named BiNPU, is designed based on a unified architecture that can efficiently process BNN modules of various types, including those with group convolution and global average pooling, in a consistent output-parallel mechanism without resource overhead. Implemented in a 28 nm FPGA, BiNPU shows the resource efficiency as high as 33.0 MOP/s/LUT, 35.3% higher than the previous state-of-the-art processor that supports even fewer module types. BiNPU performs the CIFAR10 classification task achieving 88.26% accuracy with 1.9 Mbit parameters entirely stored in on-chip memories. The BRAM usage for implementing the on-chip memories is rather smaller than those of the previous processors stored some of the parameters in off-chip memories.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4673-4677"},"PeriodicalIF":4.6000,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy With 1.9 Mbit On-Chip Parameters in a 28-nm FPGA\",\"authors\":\"Gil-Ho Kwak;Tae-Hwan Kim\",\"doi\":\"10.1109/TCSII.2024.3440965\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient processor to perform inference of binary neural networks (BNNs) is presented. The proposed processor, named BiNPU, is designed based on a unified architecture that can efficiently process BNN modules of various types, including those with group convolution and global average pooling, in a consistent output-parallel mechanism without resource overhead. Implemented in a 28 nm FPGA, BiNPU shows the resource efficiency as high as 33.0 MOP/s/LUT, 35.3% higher than the previous state-of-the-art processor that supports even fewer module types. BiNPU performs the CIFAR10 classification task achieving 88.26% accuracy with 1.9 Mbit parameters entirely stored in on-chip memories. The BRAM usage for implementing the on-chip memories is rather smaller than those of the previous processors stored some of the parameters in off-chip memories.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"71 11\",\"pages\":\"4673-4677\"},\"PeriodicalIF\":4.6000,\"publicationDate\":\"2024-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10632073/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10632073/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
BiNPU: A 33.0 MOP/s/LUT Binary Neural Network Inference Processor Showing 88.26% CIFAR10 Accuracy With 1.9 Mbit On-Chip Parameters in a 28-nm FPGA
An efficient processor to perform inference of binary neural networks (BNNs) is presented. The proposed processor, named BiNPU, is designed based on a unified architecture that can efficiently process BNN modules of various types, including those with group convolution and global average pooling, in a consistent output-parallel mechanism without resource overhead. Implemented in a 28 nm FPGA, BiNPU shows the resource efficiency as high as 33.0 MOP/s/LUT, 35.3% higher than the previous state-of-the-art processor that supports even fewer module types. BiNPU performs the CIFAR10 classification task achieving 88.26% accuracy with 1.9 Mbit parameters entirely stored in on-chip memories. The BRAM usage for implementing the on-chip memories is rather smaller than those of the previous processors stored some of the parameters in off-chip memories.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.