{"title":"动态电压扩展下 22 纳米 FD-SOI nMOSFET 的阈值电压衰减建模","authors":"Yibo Hu;Hao Ge;Zhipeng Ren;Yizhe Yin;Jing Chen","doi":"10.1109/TDMR.2024.3414181","DOIUrl":null,"url":null,"abstract":"In this work, we investigated a compact model for characterizing Positive Bias Temperature Instability (PBTI) in 22nm FD-SOI nMOSFETs under dynamic voltage scaling (DVS). This model exhibits high flexibility in predicting PBTI-related threshold voltage degradation in both DC and DVS operations. We measured the impact of time-varying stress and recovery bias conditions, revealing a robust correlation between degradation and relaxation. We integrated the coupling of interface traps and fixed charges into the model, which is deemed a significant contribution. As a result, the model demonstrates high predictive accuracy across various stress conditions, including DC/AC, multiple cycles, and different duty cycles.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"463-465"},"PeriodicalIF":2.5000,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Modeling of Threshold Voltage Degradation of 22nm FD-SOI nMOSFETs Under Dynamic Voltage Scaling\",\"authors\":\"Yibo Hu;Hao Ge;Zhipeng Ren;Yizhe Yin;Jing Chen\",\"doi\":\"10.1109/TDMR.2024.3414181\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we investigated a compact model for characterizing Positive Bias Temperature Instability (PBTI) in 22nm FD-SOI nMOSFETs under dynamic voltage scaling (DVS). This model exhibits high flexibility in predicting PBTI-related threshold voltage degradation in both DC and DVS operations. We measured the impact of time-varying stress and recovery bias conditions, revealing a robust correlation between degradation and relaxation. We integrated the coupling of interface traps and fixed charges into the model, which is deemed a significant contribution. As a result, the model demonstrates high predictive accuracy across various stress conditions, including DC/AC, multiple cycles, and different duty cycles.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"24 3\",\"pages\":\"463-465\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2024-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10556611/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10556611/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Modeling of Threshold Voltage Degradation of 22nm FD-SOI nMOSFETs Under Dynamic Voltage Scaling
In this work, we investigated a compact model for characterizing Positive Bias Temperature Instability (PBTI) in 22nm FD-SOI nMOSFETs under dynamic voltage scaling (DVS). This model exhibits high flexibility in predicting PBTI-related threshold voltage degradation in both DC and DVS operations. We measured the impact of time-varying stress and recovery bias conditions, revealing a robust correlation between degradation and relaxation. We integrated the coupling of interface traps and fixed charges into the model, which is deemed a significant contribution. As a result, the model demonstrates high predictive accuracy across various stress conditions, including DC/AC, multiple cycles, and different duty cycles.
期刊介绍：
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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