类 TPU 架构中作为全局缓冲器的 3-D 可堆叠 FeRAM 的耐用性感知编译器

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-06-17 DOI:10.1109/TVLSI.2024.3412631
Yuan-Chun Luo;Anni Lu;Yandong Luo;Sou-Chi Chang;Uygar Avci;Shimeng Yu
{"title":"类 TPU 架构中作为全局缓冲器的 3-D 可堆叠 FeRAM 的耐用性感知编译器","authors":"Yuan-Chun Luo;Anni Lu;Yandong Luo;Sou-Chi Chang;Uygar Avci;Shimeng Yu","doi":"10.1109/TVLSI.2024.3412631","DOIUrl":null,"url":null,"abstract":"Emerging nonvolatile memories as embedded memories offer low leakage power and high memory density, compared to the static random access memory (SRAM) and embedded dynamic random access memory (eDRAM) at the same technology node. However, the emerging memories generally suffer from limited cycling endurance. For read/write intensive applications, the limited endurance could become a bottleneck that limits the lifetime of the overall system. In this work, Intel’s reported prototype 3-D stackable ferroelectric random access memory (FeRAM) is considered as the global buffer memory of a tensor-processing-unit (TPU)-like architecture. An endurance-aware compiler is proposed to evaluate the maximum number of deep neural network (DNN) trainings considering the experimentally measured endurance limit. In addition, the proposed compiler applies two strategies to alleviate the endurance issue. The first strategy is wear leveling, and the second strategy is the dual-mode operation between volatile and nonvolatile modes. The maximum numbers of trainings increase by \n<inline-formula> <tex-math>$6\\times $ </tex-math></inline-formula>\n to \n<inline-formula> <tex-math>$300\\times $ </tex-math></inline-formula>\n and \n<inline-formula> <tex-math>$4\\times $ </tex-math></inline-formula>\n to \n<inline-formula> <tex-math>$58\\times $ </tex-math></inline-formula>\n thanks to the wear-leveling and dual-mode operations, respectively. Finally, a guideline of the system endurance (maximum number of trainings) is provided with given memory device endurance to bridge the gap between memory device engineers and system designers.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 9","pages":"1696-1703"},"PeriodicalIF":2.8000,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture\",\"authors\":\"Yuan-Chun Luo;Anni Lu;Yandong Luo;Sou-Chi Chang;Uygar Avci;Shimeng Yu\",\"doi\":\"10.1109/TVLSI.2024.3412631\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Emerging nonvolatile memories as embedded memories offer low leakage power and high memory density, compared to the static random access memory (SRAM) and embedded dynamic random access memory (eDRAM) at the same technology node. However, the emerging memories generally suffer from limited cycling endurance. For read/write intensive applications, the limited endurance could become a bottleneck that limits the lifetime of the overall system. In this work, Intel’s reported prototype 3-D stackable ferroelectric random access memory (FeRAM) is considered as the global buffer memory of a tensor-processing-unit (TPU)-like architecture. An endurance-aware compiler is proposed to evaluate the maximum number of deep neural network (DNN) trainings considering the experimentally measured endurance limit. In addition, the proposed compiler applies two strategies to alleviate the endurance issue. The first strategy is wear leveling, and the second strategy is the dual-mode operation between volatile and nonvolatile modes. The maximum numbers of trainings increase by \\n<inline-formula> <tex-math>$6\\\\times $ </tex-math></inline-formula>\\n to \\n<inline-formula> <tex-math>$300\\\\times $ </tex-math></inline-formula>\\n and \\n<inline-formula> <tex-math>$4\\\\times $ </tex-math></inline-formula>\\n to \\n<inline-formula> <tex-math>$58\\\\times $ </tex-math></inline-formula>\\n thanks to the wear-leveling and dual-mode operations, respectively. Finally, a guideline of the system endurance (maximum number of trainings) is provided with given memory device endurance to bridge the gap between memory device engineers and system designers.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"32 9\",\"pages\":\"1696-1703\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10559765/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10559765/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

与相同技术节点的静态随机存取存储器(SRAM)和嵌入式动态随机存取存储器(eDRAM)相比,作为嵌入式存储器的新兴非易失性存储器具有漏电功率低、存储器密度高等特点。然而,新兴存储器普遍存在循环耐久性有限的问题。对于读/写密集型应用,有限的耐用性可能成为限制整个系统寿命的瓶颈。在这项工作中,英特尔公司报告的三维可堆叠铁电随机存取存储器(FeRAM)原型被视为类似张量处理单元(TPU)架构的全局缓冲存储器。考虑到实验测得的耐用性限制,提出了一种耐用性感知编译器,用于评估深度神经网络(DNN)训练的最大次数。此外,该编译器还采用了两种策略来缓解耐久性问题。第一种策略是损耗均衡,第二种策略是易失性和非易失性模式之间的双模式操作。由于采用了磨平和双模式操作,最大训练次数分别从 6 次增加到 300 次和 4 次增加到 58 次。最后,在给定内存设备耐久性的情况下,提供了系统耐久性(最大训练次数)指南,以缩小内存设备工程师和系统设计师之间的差距。
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Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture
Emerging nonvolatile memories as embedded memories offer low leakage power and high memory density, compared to the static random access memory (SRAM) and embedded dynamic random access memory (eDRAM) at the same technology node. However, the emerging memories generally suffer from limited cycling endurance. For read/write intensive applications, the limited endurance could become a bottleneck that limits the lifetime of the overall system. In this work, Intel’s reported prototype 3-D stackable ferroelectric random access memory (FeRAM) is considered as the global buffer memory of a tensor-processing-unit (TPU)-like architecture. An endurance-aware compiler is proposed to evaluate the maximum number of deep neural network (DNN) trainings considering the experimentally measured endurance limit. In addition, the proposed compiler applies two strategies to alleviate the endurance issue. The first strategy is wear leveling, and the second strategy is the dual-mode operation between volatile and nonvolatile modes. The maximum numbers of trainings increase by $6\times $ to $300\times $ and $4\times $ to $58\times $ thanks to the wear-leveling and dual-mode operations, respectively. Finally, a guideline of the system endurance (maximum number of trainings) is provided with given memory device endurance to bridge the gap between memory device engineers and system designers.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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