An Ultrawide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection

An ultrawide load-range output capacitor-less digital LDO (DLDO) with an adaptive gate modulation scheme is described. The proposed DLDO is primarily regulated by digital codes with a synchronous clock signal while the gate driving level is dynamically adjusted according to the load current level. The proposed gate modulation scheme can significantly widen the dynamic range of load current and reduce the output voltage ripple. In addition, an asynchronous droop detection circuit, coupled with adaptive gate modulation, is added to improve the voltage droop and ensure fast recovery from load transients. The proposed DLDO was fabricated in 28-nm CMOS process. The dynamic load range of 57 $143\times $ (1.4– $80~\mu $ A) is achieved and the output voltage ripple of under 17 mV is measured across the entire load current range. A response time of less than 10 ns and a recovery time of less than 30 ns are measured in various load transient conditions.