Mohammadreza Abbasi;Tanya Thapliyal;Syed Mohammad Ashab Uddin;Wooram Lee
{"title":"45 纳米 RFSOI 中输出功率大于 10 dBm、效率大于 12% 的 114-126-GHz 倍频器","authors":"Mohammadreza Abbasi;Tanya Thapliyal;Syed Mohammad Ashab Uddin;Wooram Lee","doi":"10.1109/LMWT.2024.3424729","DOIUrl":null,"url":null,"abstract":"This letter presents a D-band frequency doubler integrated with a power amplifier to achieve high output power and efficiency in 45 nm RFSOI. The proposed frequency doubler generates a broadband fully differential output by extracting the second-order harmonic from the shared source and drain nodes of a push-push differential pair and amplifying it through a common gate (CG) stage. The power amplifier exploits a novel device, the ADNFET developed by GlobalFoundries, which exhibits improved breakdown voltage for higher output power and efficiency. The fabricated IC integrates the proposed frequency doubler and power amplifier and reports the measured saturation output power greater than 10 dBm (11.7 dBm at 116 GHz) with a peak drain efficiency higher than 12% (15% at 116 GHz) from 114 to 126 GHz.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 9","pages":"1107-1110"},"PeriodicalIF":0.0000,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 114–126-GHz Frequency Doubler With >10 dBm Output Power and >12% Efficiency in 45 nm RFSOI\",\"authors\":\"Mohammadreza Abbasi;Tanya Thapliyal;Syed Mohammad Ashab Uddin;Wooram Lee\",\"doi\":\"10.1109/LMWT.2024.3424729\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a D-band frequency doubler integrated with a power amplifier to achieve high output power and efficiency in 45 nm RFSOI. The proposed frequency doubler generates a broadband fully differential output by extracting the second-order harmonic from the shared source and drain nodes of a push-push differential pair and amplifying it through a common gate (CG) stage. The power amplifier exploits a novel device, the ADNFET developed by GlobalFoundries, which exhibits improved breakdown voltage for higher output power and efficiency. The fabricated IC integrates the proposed frequency doubler and power amplifier and reports the measured saturation output power greater than 10 dBm (11.7 dBm at 116 GHz) with a peak drain efficiency higher than 12% (15% at 116 GHz) from 114 to 126 GHz.\",\"PeriodicalId\":73297,\"journal\":{\"name\":\"IEEE microwave and wireless technology letters\",\"volume\":\"34 9\",\"pages\":\"1107-1110\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-07-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE microwave and wireless technology letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10599940/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"0\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10599940/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 114–126-GHz Frequency Doubler With >10 dBm Output Power and >12% Efficiency in 45 nm RFSOI
This letter presents a D-band frequency doubler integrated with a power amplifier to achieve high output power and efficiency in 45 nm RFSOI. The proposed frequency doubler generates a broadband fully differential output by extracting the second-order harmonic from the shared source and drain nodes of a push-push differential pair and amplifying it through a common gate (CG) stage. The power amplifier exploits a novel device, the ADNFET developed by GlobalFoundries, which exhibits improved breakdown voltage for higher output power and efficiency. The fabricated IC integrates the proposed frequency doubler and power amplifier and reports the measured saturation output power greater than 10 dBm (11.7 dBm at 116 GHz) with a peak drain efficiency higher than 12% (15% at 116 GHz) from 114 to 126 GHz.