Custom RISC-V architecture incorporating memristive in-memory computing

Due to the rise in data-intensive applications, the von Neumann bottleneck is increasingly restricting modern computer architectures, resulting to latency and energy consumption. Addressing this challenge necessitates a CMOS-compatible solution with high energy efficiency and significant parallelism. Utilizing resistive switching components within a 1T1R crossbar array and the application of Stanford RRAM model, this paper suggests an original method for in-memory computing. Moreover, this work shows a new way to advance the popular RISC-V architecture by including memristive crossbar array. It does this by adding a custom instruction set, special hardware blocks, and the Scouting Logic Scheme. These modifications serve both as a comprehensive testbed for the memory system and a proof of concept for the future integration of memristors in computing architectures. The proposed design undergoes extensive testing and power analysis to validate its functionality and performance under various conditions. The results demonstrate significant improvements in computational efficiency and energy savings, highlighting the potential of memristor-based in-memory computing systems to overcome current architectural limitations.