VTSMOC：针对高维模拟电路合成的高效 Voronoi 树搜索助推多目标贝叶斯优化法（带约束条件

IF 2.7 3区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Pub Date : 2024-09-06 DOI:10.1109/tcad.2024.3455932

Aidong Zhao, Ruiyu Lyu, Xuyang Zhao, Zhaori Bi, Fan Yang, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng

引用次数: 0

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

VTSMOC: An Efficient Voronoi Tree Search Boosted Multi-objective Bayesian Optimization with Constraints for High-dimensional Analog Circuit Synthesis

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 工程技术-工程：电子与电气

CiteScore

5.60

自引率

13.80%

发文量

500

审稿时长

7 months

期刊介绍： The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.

期刊最新文献

Table of Contents NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy FreePrune: An Automatic Pruning Framework Across Various Granularities Based on Training-Free Evaluation CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs