Geometric Variability‐Aware Thermal Characteristics Modeling of Nanoscale Silicon Gate‐All‐around Nanowire Transistor

Thermal management becomes increasingly important in silicon gate‐all‐around (GAA) field‐effect transistor (FETs) for 3 nm technology node and beyond. The channel thermal conductivity significantly differs from bulk silicon. Precise determination of thermal conductivity is crucial for device evaluation and optimization. This study investigates the thermal conductivity of silicon nanowires, examining the complex interplay between size and channel orientation. The conventional nonequilibrium molecular dynamics (NEMD) method is used with the standard Stillinger–Weber potential at the atomic scale. The results indicate that the thermal conductivity of silicon nanowires along the [100] direction increases monotonically with both length (L) and cross‐sectional side length (D). Conversely, the [110] direction exhibits nonmonotonic variation in thermal conductivity with D, due to increased acoustic–optic phonon scattering. For GAA FET devices with a silicon nanowire channel of L = 20 nm and D = 5 nm, the NEMD calculations yield thermal conductivities of 10.8 W m·K−1 for the [100] direction and 25.3 W m·K−1 for the [110] direction. Subsequently, the self‐heating effect (SHE) in silicon nanowire GAA FETs by technology computer‐aided design with the modified channel conductivity is analyzed. The results suggest that silicon nanowires with the [110] transport direction are more suitable for device design.