揭示用于统一 PUF 和 TRNG 架构的锁相环振荡器的真正威力

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-04 DOI:10.1109/TVLSI.2024.3448503
Riccardo Della Sala;Davide Bellizia;Giuseppe Scotti
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引用次数: 0

摘要

这项工作提出了一种利用锁存环振荡器(LRO)作为可重构熵源的新建议,优于现有的物理不可克隆函数(puf)和真随机数发生器(trng)。本文首次提出了PUF的工作原理和数学模型,并在FPGA上进行了性能测试。提出的基于lro的PUF比FPGA上最先进的PUF紧凑2倍。重新审视了LRO TRNG架构,并引入了基于xor树的后处理技术,将吞吐量从0.76提高到800mbit /s,为新型高吞吐量可重构熵源铺平了道路。在电源电压和温度变化下进行的NIST测试结果表明,在不同的应用中,密钥提取和安全随机数生成具有鲁棒性。这个全面的提案旨在推进紧凑和高吞吐量熵源的最新技术,以满足现代加密硬件日益增长的需求。
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Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture
This work presents a novel proposal for utilizing the latched ring oscillator (LRO) as a reconfigurable entropy source, outperforming the existing literature on both physical unclonable functions (PUFs) and true random number generators (TRNGs). The PUF working principle and mathematical model are proposed in this manuscript for the first time as well as its performance measured on FPGA. The proposed LRO-based PUF is $2\times $ more compact than state-of-the-art PUFs on FPGA. The LRO TRNG architecture has been revisited, and an XOR-tree-based postprocessing technique has been introduced to increase the throughput from 0.76 up to 800 Mbit/s, paving the way for a novel class of high-throughput reconfigurable entropy sources. The results of NIST tests carried out also under supply voltage and temperature variations have demonstrated robust key extraction and secure random number generation for different applications. This comprehensive proposal aims to advance the state of the art in compact and high-throughput entropy sources, catering to the increasing demands of modern cryptographic hardware.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information
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