{"title":"利用测量预测编码设计低复杂度量化压缩传感","authors":"Lakshmi Bhanuprakash Reddy Konduru;Vikramkumar Pudi;Balasubramanyam Appina","doi":"10.1109/TVLSI.2024.3438249","DOIUrl":null,"url":null,"abstract":"Block-based compressive sensing (BCS) has evolved as a promising method for smart devices with limited bandwidth and computing capabilities, striking a balance between image/video quality and transmission efficiency. Despite its advantages, BCS falls short in reducing bitrate compared with traditional acquisition systems, because it increases the number of bits per measurement, which leads to high storage and transmission costs. In this context, we propose a measurement predictive coding (MPC) along with the quantization method in integration with BCS named BCS-MPC; here, we have performed the quantization with bit shifts only instead of binary division. The proposed method reduces the number of bits per compressive sensing (CS) measurement as well as the transmission of the quantization step size. Furthermore, it reduces the latency and hardware resources. The proposed method improved on average +3.44 to +8.28 dB in PSNR over the current works. From the synthesis results, the proposed BCS-MPC method requires 26.11%, 18.89%, and 82.53% less area, power, and delay over the existing work. We have achieved a reduction in delay with bit-shift operations.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"288-292"},"PeriodicalIF":2.8000,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding\",\"authors\":\"Lakshmi Bhanuprakash Reddy Konduru;Vikramkumar Pudi;Balasubramanyam Appina\",\"doi\":\"10.1109/TVLSI.2024.3438249\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Block-based compressive sensing (BCS) has evolved as a promising method for smart devices with limited bandwidth and computing capabilities, striking a balance between image/video quality and transmission efficiency. Despite its advantages, BCS falls short in reducing bitrate compared with traditional acquisition systems, because it increases the number of bits per measurement, which leads to high storage and transmission costs. In this context, we propose a measurement predictive coding (MPC) along with the quantization method in integration with BCS named BCS-MPC; here, we have performed the quantization with bit shifts only instead of binary division. The proposed method reduces the number of bits per compressive sensing (CS) measurement as well as the transmission of the quantization step size. Furthermore, it reduces the latency and hardware resources. The proposed method improved on average +3.44 to +8.28 dB in PSNR over the current works. From the synthesis results, the proposed BCS-MPC method requires 26.11%, 18.89%, and 82.53% less area, power, and delay over the existing work. We have achieved a reduction in delay with bit-shift operations.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":\"33 1\",\"pages\":\"288-292\"},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-08-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10634299/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10634299/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding
Block-based compressive sensing (BCS) has evolved as a promising method for smart devices with limited bandwidth and computing capabilities, striking a balance between image/video quality and transmission efficiency. Despite its advantages, BCS falls short in reducing bitrate compared with traditional acquisition systems, because it increases the number of bits per measurement, which leads to high storage and transmission costs. In this context, we propose a measurement predictive coding (MPC) along with the quantization method in integration with BCS named BCS-MPC; here, we have performed the quantization with bit shifts only instead of binary division. The proposed method reduces the number of bits per compressive sensing (CS) measurement as well as the transmission of the quantization step size. Furthermore, it reduces the latency and hardware resources. The proposed method improved on average +3.44 to +8.28 dB in PSNR over the current works. From the synthesis results, the proposed BCS-MPC method requires 26.11%, 18.89%, and 82.53% less area, power, and delay over the existing work. We have achieved a reduction in delay with bit-shift operations.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.