利用测量预测编码设计低复杂度量化压缩传感

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-12 DOI:10.1109/TVLSI.2024.3438249
Lakshmi Bhanuprakash Reddy Konduru;Vikramkumar Pudi;Balasubramanyam Appina
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引用次数: 0

摘要

基于块的压缩感知(BCS)已经发展成为具有有限带宽和计算能力的智能设备的一种有前途的方法,在图像/视频质量和传输效率之间取得平衡。尽管具有优势,但与传统采集系统相比,BCS在降低比特率方面存在不足,因为它增加了每次测量的比特数,从而导致较高的存储和传输成本。在此背景下,我们提出了一种测量预测编码(MPC)以及与BCS集成的量化方法,称为BCS-MPC;在这里,我们只使用位移位而不是二进制除法进行量化。该方法减少了每次压缩感知(CS)测量的比特数以及量化步长的传输。此外,它还减少了延迟和硬件资源。该方法比现有方法平均提高了+3.44 ~ +8.28 dB的PSNR。从综合结果来看,本文提出的BCS-MPC方法比现有方法的面积、功耗和延迟分别减少26.11%、18.89%和82.53%。我们已经通过位移操作实现了延迟的减少。
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Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding
Block-based compressive sensing (BCS) has evolved as a promising method for smart devices with limited bandwidth and computing capabilities, striking a balance between image/video quality and transmission efficiency. Despite its advantages, BCS falls short in reducing bitrate compared with traditional acquisition systems, because it increases the number of bits per measurement, which leads to high storage and transmission costs. In this context, we propose a measurement predictive coding (MPC) along with the quantization method in integration with BCS named BCS-MPC; here, we have performed the quantization with bit shifts only instead of binary division. The proposed method reduces the number of bits per compressive sensing (CS) measurement as well as the transmission of the quantization step size. Furthermore, it reduces the latency and hardware resources. The proposed method improved on average +3.44 to +8.28 dB in PSNR over the current works. From the synthesis results, the proposed BCS-MPC method requires 26.11%, 18.89%, and 82.53% less area, power, and delay over the existing work. We have achieved a reduction in delay with bit-shift operations.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information
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