Noise Improvement and High Dynamic Range in a CMOS Image Sensor With Shift Biasing Structure

In this article, a noise improvement and dynamic range (DR) enhanced CMOS image sensor (CIS), using a shift biasing structure, is proposed. The shift biasing pixel is constructed from a conventional 4T pixel and three additional transistors, including a bias transistor (BT) and two switch transistors. The BT works as a switch to connect the source and drain to accumulate electrons in the source follower (SF) in shift biasing mode and provides an extra capacitance to enlarge the capacity of floating diffusion (FD) in low gain (LG) mode. Electron distribution and noise performance of SF are simulated to prove the function of shift biasing pixels. A prototype sensor, with a $512\times 128$ -pixel array, is fabricated with a 180 nm CIS process. Measurement shows a temporal noise of 2 e $^{-}$ is achieved, which is a 2 e $^{-}$ noise improvement compared with the reference 4T readout mode of shift biasing pixel. Additionally, an over 92 dB DR is realized by combining shift biasing mode and LG mode without any specific process or complex control circuits.