{"title":"为二维晶体管设定硅基准标准","authors":"Peng Wu, Jianfeng Jiang, Lian-Mao Peng","doi":"10.1038/s44287-024-00093-y","DOIUrl":null,"url":null,"abstract":"2D materials hold great promise for logic scaling beyond the limit of silicon MOSFET. However, in the absence of widely accepted guidelines for the performance comparison of the two technologies, it is essential to set proper standards to benchmark 2D transistors against silicon transistors.","PeriodicalId":501701,"journal":{"name":"Nature Reviews Electrical Engineering","volume":"1 10","pages":"629-631"},"PeriodicalIF":0.0000,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Setting a standard for benchmarking 2D transistors with silicon\",\"authors\":\"Peng Wu, Jianfeng Jiang, Lian-Mao Peng\",\"doi\":\"10.1038/s44287-024-00093-y\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"2D materials hold great promise for logic scaling beyond the limit of silicon MOSFET. However, in the absence of widely accepted guidelines for the performance comparison of the two technologies, it is essential to set proper standards to benchmark 2D transistors against silicon transistors.\",\"PeriodicalId\":501701,\"journal\":{\"name\":\"Nature Reviews Electrical Engineering\",\"volume\":\"1 10\",\"pages\":\"629-631\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nature Reviews Electrical Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.nature.com/articles/s44287-024-00093-y\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nature Reviews Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://www.nature.com/articles/s44287-024-00093-y","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Setting a standard for benchmarking 2D transistors with silicon
2D materials hold great promise for logic scaling beyond the limit of silicon MOSFET. However, in the absence of widely accepted guidelines for the performance comparison of the two technologies, it is essential to set proper standards to benchmark 2D transistors against silicon transistors.
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