采用双斜率时间放大器的 12 ps 精度两步时-数转换器,在 180 nm CMOS 上以 1 MS/s 的速度消耗 434 $\mu$W

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-13 DOI:10.1109/TCSI.2024.3454793
Xinchi Xu;Yonggang Wang;Yonghang Zhou;Zhengqi Song;Bo Wu;Xin Lin
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By adopting the improved TA circuit into the TDC with a high gain, adjustable output offsets, and good linearity, the TDC measurement precision is guaranteed. In addition, a new DLL structure is proposed to stabilize the TDL against process, voltage, and temperature (PVT) variations with less power consumption. Benefiting from the proposed residue extraction method and DLL structure, the TDC exhibits low power consumption. To verify the TDC design, a prototype chip with two TDC channels is fabricated in GlobalFoundries (GF) 180 nm CMOS technology for performance evaluation. With a system clock of 150 MHz, it has a resolution (LSB) of 16.5 ps and a maximum sample rate of 6 MS/s. The differential nonlinearity (DNL) error ranges from −0.98 LSB to 0.87 LSB and the integral nonlinearity error (INL) ranges from −4.21 LSB to 2.83 LSB. With a bin-by-bin calibration method, the measured TDC precision is 12.1 ps on average within the 0–20 ns time interval measurement range. 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引用次数: 0

摘要

设计了一种两步时间-数字转换器(TDC),用于超级Tau-Charm设施(STCF)中类似dirc的TOF (DTOF)探测器的高精度时间测量。通过Nutt的方法扩展测量范围,TDC时钟周期由双斜率时间放大器(TA)连接的两条压控抽头延迟线(TDL)内插。通过将第一步TDL插值的残差用TA放大,再用第二步TDL测量,TDC分辨率显著提高到子门延迟。由于采用新方法提取残差,不需要重复TA或插入延迟,因此有效地降低了TDC功耗和转换时间。将改进后的TA电路引入到TDC中,具有高增益、输出偏置可调、线性度好等特点,保证了TDC的测量精度。此外,提出了一种新的DLL结构,以稳定TDL对工艺、电压和温度(PVT)变化的影响,同时降低功耗。基于所提出的残渣提取方法和DLL结构,TDC具有低功耗的特点。为了验证TDC设计,采用GlobalFoundries (GF) 180 nm CMOS技术制作了具有两个TDC通道的原型芯片以进行性能评估。系统时钟为150 MHz,分辨率(LSB)为16.5 ps,最大采样率为6 MS/s。微分非线性误差(DNL)范围为−0.98 ~ 0.87 LSB,积分非线性误差(INL)范围为−4.21 ~ 2.83 LSB。采用逐箱校准方法,在0-20 ns的时间间隔测量范围内,测量的上止点精度平均为12.1 ps。此外,TDC具有较低的温度灵敏度,在20℃温度范围内不需要重新校准。在1 MS/s采样率下,每个TDC通道功耗为434~\mu $ W。测试结果表明,该TDC可以在不需要大规模技术的情况下,以中等采样率和低功耗实现高精度,可以满足STCF dof探测器的要求。
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A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 μW at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier
A two-step time-to-digital converter (TDC) is designed for the high-precision time measurement of the DIRC-like TOF (DTOF) detector at the Super Tau-Charm Facility (STCF). Extending the measurement range by Nutt’s method, the TDC clock cycle is interpolated with two voltage-controlled tapped delay lines (TDL) connected by a dual-slope time amplifier (TA). By amplifying the residue from the first-step TDL-based interpolation with the TA and measuring it with the second TDL, the TDC resolution is significantly improved to sub-gate delay. Since the residue is extracted by a new method without the need of TA duplication or delay insertion, the TDC power consumption and conversion time are effectively reduced. By adopting the improved TA circuit into the TDC with a high gain, adjustable output offsets, and good linearity, the TDC measurement precision is guaranteed. In addition, a new DLL structure is proposed to stabilize the TDL against process, voltage, and temperature (PVT) variations with less power consumption. Benefiting from the proposed residue extraction method and DLL structure, the TDC exhibits low power consumption. To verify the TDC design, a prototype chip with two TDC channels is fabricated in GlobalFoundries (GF) 180 nm CMOS technology for performance evaluation. With a system clock of 150 MHz, it has a resolution (LSB) of 16.5 ps and a maximum sample rate of 6 MS/s. The differential nonlinearity (DNL) error ranges from −0.98 LSB to 0.87 LSB and the integral nonlinearity error (INL) ranges from −4.21 LSB to 2.83 LSB. With a bin-by-bin calibration method, the measured TDC precision is 12.1 ps on average within the 0–20 ns time interval measurement range. In addition, the TDC has low temperature sensitivity and does not require recalibration within a 20 ° C temperature range. Each TDC channel consumes $434~\mu $ W power at 1 MS/s sample rate. The test results confirm that the proposed TDC can achieve high precision with a moderate sample rate and low power consumption without highly scaled technologies, which can meet the requirements of the DTOF detector at STCF.
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
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