46-nA 高PSR CMOS 缓冲电压基准,工作范围为 1.2-5 V 和 $-$40 $^{circ}$C 至 125 $^{circ}$C

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-17 DOI:10.1109/TVLSI.2024.3455428
Chiara Venezia;Andrea Ballo;Alfio Dario Grasso;Alessandro Rizzo;Calogero Ribellino;Salvatore Pennisi
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引用次数: 0

摘要

提出了一种纳米级缓冲CMOS电压基准,设计用于整个工业温度范围(从$- 40~^{\circ}$ C到$125~^{\circ}$ C),输入电压范围为1.2至5 V(汽车应用)。该解决方案可在$20~^{\circ}$ C下提供390 mV,并采用具有160纳米CMOS器件的标准BCD技术实现。其特点是平均温度系数为200 ppm/°C,线路灵敏度(LS)为0.138%/V, 100 Hz时电源抑制为−83 dB。此外,该电路的芯片面积为0.146 mm2(仅参考电路占地0.043 mm2),在各种工艺和输入电压条件下(仅参考电路为25 nA)保持45 nA左右的高稳定电流消耗,同时提供630~\mu $ a的最大输出电流,负载调节为0.016 mV/ $\mu $ a。
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46-nA High-PSR CMOS Buffered Voltage Reference With 1.2–5 V and −40 ◦C to 125 ◦C Operating Range
A nanopower, buffered CMOS voltage reference designed to operate across the entire industrial temperature range (from $- 40~^{\circ }$ C to $125~^{\circ }$ C) and with an input voltage range from 1.2 to 5 V (automotive applications) is presented. The solution provides 390 mV at $20~^{\circ }$ C and is implemented in a standard BCD technology featuring 160-nm CMOS devices. It is characterized by an average temperature coefficient of 200 ppm/°C, a line sensitivity (LS) of 0.138%/V, and a power supply rejection of −83 dB at 100 Hz. In addition, the circuit occupies a die area of 0.146 mm2 (with the reference circuit alone covering 0.043 mm2) and maintains a highly stable current consumption of around 45 nA across various process and input voltage conditions (25 nA for the reference circuit alone) while providing a maximum output current of $630~\mu $ A with a load regulation of 0.016 mV/ $\mu $ A.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information
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