立体视觉处理器半全局匹配的最小池成本聚合

IF 4 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems II: Express Briefs Pub Date : 2024-09-18 DOI:10.1109/TCSII.2024.3463200
Wenyue Zhang;Pingcheng Dong;Lei Chen;Zhengyu Ma;Fengwei An
{"title":"立体视觉处理器半全局匹配的最小池成本聚合","authors":"Wenyue Zhang;Pingcheng Dong;Lei Chen;Zhengyu Ma;Fengwei An","doi":"10.1109/TCSII.2024.3463200","DOIUrl":null,"url":null,"abstract":"Semi-global matching (SGM) is a low-cost method suitable for hardware implementation, while it suffers from significant memory consumption. This brief presents a stereo-vision processor that leverages a min-pooling cost aggregation method for SGM. The min-pooling method addresses this issue by eliminating redundant values and employing an up-sampling technique to restore the original size without requiring clock domain crossing. As a result, this method effectively reduces memory usage by almost half, leading to a significant improvement in large-scale depth measurement. The experimental results demonstrate that the min-pooling method enhances the continuity of disparity maps, particularly in areas with less texture, by capturing more global information and reducing noise and discontinuities. Evaluations on the Middlebury and KITTI datasets show an average accuracy of 12.19% and 5.3%, respectively, indicating a more pronounced impact on the Middlebury dataset. Resource utilization analysis reveals a 1.6-fold increase in LUT usage and a 1.5-fold increase in register usage with min-pooling, while memory size effectively reduces memory usage by 41.2% compared to the method without min-pooling.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"258-262"},"PeriodicalIF":4.0000,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Min-Pooling Cost Aggregation for Semi-Global Matching of Stereo Vision Processor\",\"authors\":\"Wenyue Zhang;Pingcheng Dong;Lei Chen;Zhengyu Ma;Fengwei An\",\"doi\":\"10.1109/TCSII.2024.3463200\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Semi-global matching (SGM) is a low-cost method suitable for hardware implementation, while it suffers from significant memory consumption. This brief presents a stereo-vision processor that leverages a min-pooling cost aggregation method for SGM. The min-pooling method addresses this issue by eliminating redundant values and employing an up-sampling technique to restore the original size without requiring clock domain crossing. As a result, this method effectively reduces memory usage by almost half, leading to a significant improvement in large-scale depth measurement. The experimental results demonstrate that the min-pooling method enhances the continuity of disparity maps, particularly in areas with less texture, by capturing more global information and reducing noise and discontinuities. Evaluations on the Middlebury and KITTI datasets show an average accuracy of 12.19% and 5.3%, respectively, indicating a more pronounced impact on the Middlebury dataset. Resource utilization analysis reveals a 1.6-fold increase in LUT usage and a 1.5-fold increase in register usage with min-pooling, while memory size effectively reduces memory usage by 41.2% compared to the method without min-pooling.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 1\",\"pages\":\"258-262\"},\"PeriodicalIF\":4.0000,\"publicationDate\":\"2024-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10683721/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10683721/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Min-Pooling Cost Aggregation for Semi-Global Matching of Stereo Vision Processor
Semi-global matching (SGM) is a low-cost method suitable for hardware implementation, while it suffers from significant memory consumption. This brief presents a stereo-vision processor that leverages a min-pooling cost aggregation method for SGM. The min-pooling method addresses this issue by eliminating redundant values and employing an up-sampling technique to restore the original size without requiring clock domain crossing. As a result, this method effectively reduces memory usage by almost half, leading to a significant improvement in large-scale depth measurement. The experimental results demonstrate that the min-pooling method enhances the continuity of disparity maps, particularly in areas with less texture, by capturing more global information and reducing noise and discontinuities. Evaluations on the Middlebury and KITTI datasets show an average accuracy of 12.19% and 5.3%, respectively, indicating a more pronounced impact on the Middlebury dataset. Resource utilization analysis reveals a 1.6-fold increase in LUT usage and a 1.5-fold increase in register usage with min-pooling, while memory size effectively reduces memory usage by 41.2% compared to the method without min-pooling.
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来源期刊
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程:电子与电气
CiteScore
7.90
自引率
20.50%
发文量
883
审稿时长
3.0 months
期刊介绍: TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.
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