基于 SiPh 的 112 Gb/s、-10 dBm 灵敏度、+5 dBm 过载接收器前端，采用 22-nm FDSOI 封装

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2024-09-11 DOI:10.1109/LSSC.2024.3457775

Mahdi Parvizi;Bahar Jalali;Toshi Omori;John Rogers;Li Chen;Long Chen;Ricardo Aroca

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引用次数: 0

摘要

本文展示了一种基于硅光子（SiPh）的 112 Gb/s PAM4 光接收器前端，它采用新型单端跨阻抗放大器（TIA）架构，可分别实现 -10 和 +5 dBm 输入光调制幅度（OMA）灵敏度和过载。为实现这一目标，提出了一种过载缓解电路，以打破并联反馈 CMOS TIA 噪声和线性度之间的平衡。该 TIA 经过优化，可分别在最小和最大输入 OMA 条件下提供最佳灵敏度和线性度性能。该 TIA 采用 22-nm FDSOI 技术实现，专为 112 Gb/s PAM4 光链路而设计，实现了超过 +15 dBm 的 OMA 范围，输入参考噪声为 11 pA/ $surd $Hz，而 1.8 V 电源的功耗仅为 155 mW。

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A 112-Gb/s, -10 dBm Sensitivity, +5 dBm Overload, and SiPh-Based Receiver Frontend in 22-nm FDSOI

This letter demonstrates a Si-Photonic (SiPh)-based 112 Gb/s PAM4 optical receiver frontend using novel single-ended transimpedance amplifier (TIA) architecture that achieves −10 and +5 dBm input optical modulation amplitude (OMA) sensitivity and overload, respectively. To achieve that an overload mitigation circuit is proposed to break the tradeoff between noise and linearity of the shunt feedback CMOS TIAs. The TIA is optimized to provide the best sensitivity and linearity performance at minimum and maximum input OMA, respectively. Implemented in 22-nm FDSOI technology, and designed for 112 Gb/s PAM4 optical links, the TIA achieves more than +15 dBm OMA range with 11 pA/

$\surd $

Hz input referred noise while burning only 155 mW from an 1.8-V supply.

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