RED-SEA 项目:建立新一代欧洲互连网

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Microprocessors and Microsystems Pub Date : 2024-09-16 DOI:10.1016/j.micpro.2024.105102
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引用次数: 0

摘要

RED-SEA 是一个 H2020 EuroHPC 项目,其主要目标是利用与标准成熟技术(以太网)相关的欧洲互联技术(BXI)、以前的欧盟资助计划以及开放标准和兼容 API,通过经济上可行、技术上高效的互联技术,为新一代欧洲互联技术做好准备,使其能够为未来的欧盟超大规模系统提供动力。为实现这一目标,RED-SEA 项目围绕四个关键支柱展开:(i) 网络架构和工作负载要求--互连协同设计--旨在优化与其他 EuroHPC 项目和 EPI 处理器的匹配;(ii) 开发高性能、低延迟、与以太网无缝连接的桥接器;(iii) 高效网络资源管理,包括拥塞和服务质量;(iv) 在网络边缘实现端到端功能。本文介绍了在实现项目最终目标的过程中,每个关键支柱在项目中期取得的主要成就和成果。在这方面,我们可以强调(i) 网络要求和架构的定义,以及基准和应用清单;(ii) 除了最初计划的 IP 进展外,BXI3 架构已发展到在低层次上支持本地以太网,从而降低了复杂性,在成本优化和功耗方面具有优势;(iii) 目标应用的拥塞特征,以及通过优化集体通信基元、注入节流和自适应路由来减少拥塞的建议;以及 (iv) 低延迟高信息速率端点功能及其与新开放技术的连接。
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RED-SEA Project: Towards a new-generation European interconnect
RED-SEA is a H2020 EuroHPC project, whose main objective is to prepare a new-generation European Interconnect, capable of powering the EU Exascale systems to come, through an economically viable and technologically efficient interconnect, leveraging European interconnect technology (BXI) associated with standard and mature technology (Ethernet), previous EU-funded initiatives, as well as open standards and compatible APIs.
To achieve this objective, the RED-SEA project is being carried out around four key pillars: (i) network architecture and workload requirements-interconnects co-design – aiming at optimizing the fit with the other EuroHPC projects and with the EPI processors; (ii) development of a high-performance, low-latency, seamless bridge with Ethernet; (iii) efficient network resource management, including congestion and Quality-of-Service; and (iv) end-to-end functions implemented at the network edges.
This paper presents key achievements and results at the midterm of the project for each key pillar in the way to reach the final project objective. In this regard we can highlight: (i) The definition of the network requirements and architecture as well as a list of benchmarks and applications; (ii) In addition to initially planned IPs progress, BXI3 architecture has evolved to support natively Ethernet at low level, resulting in reduced complexity, with advantages in terms of cost optimization, and power consumption; (iii) The congestion characterization of target applications and proposals to reduce this congestion by the optimization of collective communication primitives, injection throttling and adaptive routing; and (iv) the low-latency high-message rate endpoint functions and their connection with new open technologies.
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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
期刊最新文献
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