{"title":"使用无源正交前端、双面双平衡级联混频器和双变压器耦合 D 类 VCO 的 167-$\\mu$W 71.7-dB SFDR 2.4-GHz BLE 接收器","authors":"Haijun Shao;Rui P. Martins;Pui-In Mak","doi":"10.1109/JSSC.2024.3462093","DOIUrl":null,"url":null,"abstract":"This article reports a 2.4-GHz Bluetooth low-energy (BLE) receiver with a number of passive-intensive RF functions to improve power efficiency and blocker resilience. It features a passive quadrature front end (QFE) built with a hybrid coupler plus two step-up transformers. They passively provide input-impedance matching, voltage gain, and single-ended-to-differential-I/Q RF generation. The four-phase RF outputs simplify the LO generator into a 2.4-GHz class-D voltage-controlled oscillator (VCO) that has an intrinsically boosted output swing, averting the power-hungry divider-by-2 and LO buffers. The frequency down-conversion based on a double-sided double-balanced (DSDB) cascaded mixer offers a high passive gain to reduce the noise and power consumption of the baseband (BB) circuitry while securing a high spurious-free dynamic range (SFDR) to tolerate the out-of-band (OOB) blockers. The BB circuitry is a power-efficient hybrid low-IF filter that employs a 2nd-order active-feedback notching to enhance the 1st-adjacent channel rejection. Fabricated in 28-nm CMOS, the BLE receiver exhibits a maximum RF-to-IF gain of 71 dB. The noise figure (NF) is 8.5 dB and the OOB-IIP3 is 20.1 dBm; they correspond to a 71.7-dB SFDR for a 2-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR\n<inline-formula> <tex-math>$_{\\min }$ </tex-math></inline-formula>\n). The VCO exhibits a phase noise (PN) of −110/−119.1/−131 dBc/Hz at 1-/2.5-/10-MHz offset, corresponding to a figure of merit (FOM) of 188/189/189.1 dBc/Hz, respectively. The total power consumption of the receiver, including the VCO, is \n<inline-formula> <tex-math>$167~{\\mu }$ </tex-math></inline-formula>\nW.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"3980-3992"},"PeriodicalIF":4.6000,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 167- μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO\",\"authors\":\"Haijun Shao;Rui P. Martins;Pui-In Mak\",\"doi\":\"10.1109/JSSC.2024.3462093\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article reports a 2.4-GHz Bluetooth low-energy (BLE) receiver with a number of passive-intensive RF functions to improve power efficiency and blocker resilience. It features a passive quadrature front end (QFE) built with a hybrid coupler plus two step-up transformers. They passively provide input-impedance matching, voltage gain, and single-ended-to-differential-I/Q RF generation. The four-phase RF outputs simplify the LO generator into a 2.4-GHz class-D voltage-controlled oscillator (VCO) that has an intrinsically boosted output swing, averting the power-hungry divider-by-2 and LO buffers. The frequency down-conversion based on a double-sided double-balanced (DSDB) cascaded mixer offers a high passive gain to reduce the noise and power consumption of the baseband (BB) circuitry while securing a high spurious-free dynamic range (SFDR) to tolerate the out-of-band (OOB) blockers. The BB circuitry is a power-efficient hybrid low-IF filter that employs a 2nd-order active-feedback notching to enhance the 1st-adjacent channel rejection. Fabricated in 28-nm CMOS, the BLE receiver exhibits a maximum RF-to-IF gain of 71 dB. The noise figure (NF) is 8.5 dB and the OOB-IIP3 is 20.1 dBm; they correspond to a 71.7-dB SFDR for a 2-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR\\n<inline-formula> <tex-math>$_{\\\\min }$ </tex-math></inline-formula>\\n). The VCO exhibits a phase noise (PN) of −110/−119.1/−131 dBc/Hz at 1-/2.5-/10-MHz offset, corresponding to a figure of merit (FOM) of 188/189/189.1 dBc/Hz, respectively. The total power consumption of the receiver, including the VCO, is \\n<inline-formula> <tex-math>$167~{\\\\mu }$ </tex-math></inline-formula>\\nW.\",\"PeriodicalId\":13129,\"journal\":{\"name\":\"IEEE Journal of Solid-state Circuits\",\"volume\":\"59 12\",\"pages\":\"3980-3992\"},\"PeriodicalIF\":4.6000,\"publicationDate\":\"2024-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of Solid-state Circuits\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10701049/\",\"RegionNum\":1,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10701049/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了一种 2.4 GHz 低功耗蓝牙 (BLE) 接收器,它具有许多无源密集型射频功能,可提高能效和抗阻塞性。它采用无源正交前端 (QFE),内置一个混合耦合器和两个升压变压器。它们无源提供输入阻抗匹配、电压增益和单端到差分 I/Q 射频生成。四相射频输出将 LO 发生器简化为 2.4 GHz 的 D 类压控振荡器 (VCO),该振荡器具有固有的升压输出摆幅,避免了耗电的 2 分频器和 LO 缓冲器。基于双面双平衡(DSDB)级联混频器的频率下变频具有较高的无源增益,可降低基带(BB)电路的噪声和功耗,同时确保较高的无杂散动态范围(SFDR),以承受带外(OOB)阻塞。基带电路是一种高能效混合低中频滤波器,采用二阶有源反馈陷波来增强一相邻信道抑制能力。BLE 接收器采用 28 纳米 CMOS 制造,最大射频到中频增益为 71 dB。噪声系数(NF)为 8.5 dB,OOB-IIP3 为 20.1 dBm;对应于 2 MHz BLE 信道的 71.7 dB SFDR 和 10 dB 最小信噪比(SNR $_{\min }$ )。在 1-/2.5-/10-MHz 偏移时,VCO 的相位噪声 (PN) 为-110/-119.1/-131 dBc/Hz,分别相当于 188/189/189.1 dBc/Hz。接收器(包括 VCO)的总功耗为 167~{\mu }$ W。
A 167- μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO
This article reports a 2.4-GHz Bluetooth low-energy (BLE) receiver with a number of passive-intensive RF functions to improve power efficiency and blocker resilience. It features a passive quadrature front end (QFE) built with a hybrid coupler plus two step-up transformers. They passively provide input-impedance matching, voltage gain, and single-ended-to-differential-I/Q RF generation. The four-phase RF outputs simplify the LO generator into a 2.4-GHz class-D voltage-controlled oscillator (VCO) that has an intrinsically boosted output swing, averting the power-hungry divider-by-2 and LO buffers. The frequency down-conversion based on a double-sided double-balanced (DSDB) cascaded mixer offers a high passive gain to reduce the noise and power consumption of the baseband (BB) circuitry while securing a high spurious-free dynamic range (SFDR) to tolerate the out-of-band (OOB) blockers. The BB circuitry is a power-efficient hybrid low-IF filter that employs a 2nd-order active-feedback notching to enhance the 1st-adjacent channel rejection. Fabricated in 28-nm CMOS, the BLE receiver exhibits a maximum RF-to-IF gain of 71 dB. The noise figure (NF) is 8.5 dB and the OOB-IIP3 is 20.1 dBm; they correspond to a 71.7-dB SFDR for a 2-MHz BLE channel and a 10-dB minimum signal-to-noise ratio (SNR
$_{\min }$
). The VCO exhibits a phase noise (PN) of −110/−119.1/−131 dBc/Hz at 1-/2.5-/10-MHz offset, corresponding to a figure of merit (FOM) of 188/189/189.1 dBc/Hz, respectively. The total power consumption of the receiver, including the VCO, is
$167~{\mu }$
W.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.