LLD:针对 3-D TLC NAND 闪存的 LDPC 硬解码轻量级延迟降低方案

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-09-16 DOI:10.1109/TCSI.2024.3438789
Debao Wei;Yongchao Wang;Hua Feng;Huqi Xiang;Liyan Qiao
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引用次数: 0

摘要

低密度奇偶校验码(LDPC)已被广泛用于显著提高 3-D NAND 闪存的可靠性。然而,在数据的原始比特错误率(RBER)较高的情况下,它不仅需要更多的感应级,还需要大量的迭代,从而导致明显的读取延迟问题。为了缓解这一挑战,本文引入了一种创新的轻量级延迟降低(LLD)方案。首先,通过研究迭代次数与硬决策层(HDL)之间的相关性,建立了一个封装迭代与偏移量之间关系的功能模型。在此模型的基础上,提出了全字线延迟降低(AWLD)方案。为了进一步降低延迟,我们对闪存块内不同字线之间的相似性进行了深入分析,从而开发出一种优化的单字线轻量级延迟降低(OWLLD)方案。针对随机读取小数据量的情况,深入研究了不同重叠区域函数模型之间的相互作用,最终提出了进一步优化的单页轻量级延迟降低(OPLLD)方案。实验结果表明,与传统算法相比,OPLLD 方案可将 LDPC 的迭代性能提高 94.63%,将延迟降低 66.89%,同时将存储和计算开销降至最低。这清楚地表明,所提出的方案大大提高了闪存中 LDPC 的读取延迟性能。
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LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory
The low-density parity-check code (LDPC) has been widely used to significantly enhance the reliability of 3-D NAND flash memory. However, in cases where the raw bit error rate (RBER) of the data is high, it not only demands more sense levels but also requires a large number of iterations, leading to a notable read latency issue. To mitigate this challenge, this paper introduces an innovative lightweight latency decrease (LLD) scheme. Initially, by examining the correlation between the number of iterations and the hard decision level (HDL), a functional model that encapsulates the relationship between iteration and offset is established. Building upon this model, the all-wordlines latency decrease (AWLD) scheme is proposed. In an effort to further decrease latency, an in-depth analysis of the similarities among different wordlines within a flash memory block is conducted, leading to the development of an optimized one-wordline lightweight latency decrease (OWLLD) scheme. For scenarios involving random reading of small data volumes, the interplay between function models of various overlapping regions is delved into, which ultimately results in the proposal of a further optimized one-page lightweight latency decrease (OPLLD) scheme. Experimental findings reveal that the OPLLD scheme can enhance the iterative performance of LDPC by up to 94.63% and reduce latency by up to 66.89% compared to traditional algorithms, while incurring minimal storage and computational overhead. This clearly indicates that the proposed scheme substantially enhances the read latency performance of LDPC in flash memory.
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
期刊最新文献
Table of Contents IEEE Circuits and Systems Society Information TechRxiv: Share Your Preprint Research with the World! IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems—ISICAS 2024
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